US3914589A
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Four-by-four bit multiplier module having three stages of logic cells
Assignee: Raytheon Co
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Filing: 1974-05-13
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Granted: 1975-10-21
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Expires: 1994-05-13
Abstract
Abstract This invention is a logic design defining the interconnection of logic cells such as those Universal Logic Gates to implement either a 1''s complement (all positive) or a 2''s complement 4 X 4-bit binary multiplier. This multiplier generates the binary product of any two 4-bit binary numbers such that the input signals propagate serially through at most only three logic gating (cell) stages. An extension of the multiplier''s basic logic partition scheme permits design of larger multipliers in which adders and 4 X 4bit multipliers are used as building blocks. A detailed 8 X 8bit multiplier design is presented to concretely describe the approach. The ''''2''s-complement'''' 4 X 4-bit multiplier''s logic partition is almost identical to the one used in the (all positive) 4 X 4-bit multiplier design, incorporating subfunctions which are nearly all identical to their counterparts in the (all positive) multiplier.
Inventors
- 👤 Jr James R Gaskill
- 👤 Lawrence R Weill
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 22:45
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/52; G06F7/523; G06F7/53; G06F7/5324
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
380 words
A 4 by 4 bit multiplier for multiplying a first 4-digit binary number A A0 2.A1 + 4.A2 + 8.A3 by a second 4-digit binary number B B0 + 2.B1 + 4.B2 + 8. B3 to form an 8-digit binary product C C0 + 2.C1 + 4.C2 + 8.C3 + 16.C4 + 32.C5 + 64.C6 + 128. C7, said multiplier comprising: a first set of gating means for forming the individual digits S0, S1, S2, S3, S4, S5 of a 6-digit binary number S (B0 2.B1) .(A0 + 2.A1 + 4.A2 + 8.A3) S0 + 2.S1 + 4.S2 + 8.S3 + 16.S4 + 32.S,; a second set of gating means for forming the individual digits T0, T1, T2, T3, T4, T5 of a 6-digit binary number T (A0 + 3.A1 + 4.A2 + 8.A3) .(B2 + 2.B3) T0 + 2.T1 + 4.T2 + 8.T3 + 16.T4 + 32.T5; and a 6 by 4 bit adder for forming the sum of said 6-digit binary number T and a second 4-digit binary number formed from the 4 most significant digits of said 6-digit binary number S to form the 6 most significant digits of said 8-digit number, said adder comprising: first first-level gating means for forming a first intermediate logical variable X1 (S5 AND T3) OR ((S5 OR T3) AND (S4 AND T2)); second first-level gating means for forming a second intermediate logical variable X2 (S5 OR T3) AND (S4 OR T2); third first-level gating means for forming a third intermediate logical variable X3 (S3 AND T1) OR ((S3 OR T1) AND S2 AND TO); first second-level gating means responsive to said S4 and S5 digits and to said T2 and T3 digits as well as to said intermediate variable X3 for forming said digit C5; second second-level gating means responsive to said intermediate variables X1, X2, and X3 as well as to said variable T4 for forming said output digit C6; and third second-level gating means responsive to said intermediate variables X1, X2, X3 as well as to said T4 and T5 digits for forming said C7 digit; wherein said CO is identical to said SO, wherein said C1 is identical to said S1, and wherein said digits C2, C3, C4, C5, C6, and C7 are the outputs of said adder.
Claim 2
Dependent Claim
380 words
A 4 by 4 bit multiplier for multiplying a first 4-digit binary number A A0 2.A1 + 4.A2 + 8.A3 by a second 4-digit binary number B B0 + 2.B1 + 4.B2 + 8. B3 to form an 8-digit binary product C C0 + 2.C1 + 4.C2 + 8.C3 + 16.C4 + 32.C5 + 64.C6 + 128. C7, said multiplier comprising: a first set of gating means for forming the individual digits S0, S1, S2, S3, S4, S5 of a 6-digit binary number S (B0 2.B1) .(A0 + 2.A1 + 4.A2 + 8.A3) S0 + 2.S1 + 4.S2 + 8.S3 + 16.S4 + 32.S,; a second set of gating means for forming the individual digits T0, T1, T2, T3, T4, T5 of a 6-digit binary number T (A0 + 3.A1 + 4.A2 + 8.A3) .(B2 + 2.B3) T0 + 2.T1 + 4.T2 + 8.T3 + 16.T4 + 32.T5; and a 6 by 4 bit adder for forming the sum of said 6-digit binary number T and a second 4-digit binary number formed from the 4 most significant digits of said 6-digit binary number S to form the 6 most significant digits of said 8-digit number, said adder comprising: first first-level gating means for forming a first intermediate logical variable X1 (S5 AND T3) OR ((S5 OR T3) AND (S4 AND T2)); second first-level gating means for forming a second intermediate logical variable X2 (S5 OR T3) AND (S4 OR T2); third first-level gating means for forming a third intermediate logical variable X3 (S3 AND T1) OR ((S3 OR T1) AND S2 AND TO); first second-level gating means responsive to said S4 and S5 digits and to said T2 and T3 digits as well as to said intermediate variable X3 for forming said digit C5; second second-level gating means responsive to said intermediate variables X1, X2, and X3 as well as to said variable T4 for forming said output digit C6; and third second-level gating means responsive to said intermediate variables X1, X2, X3 as well as to said T4 and T5 digits for forming said C7 digit; wherein said CO is identical to said SO, wherein said C1 is identical to said S1, and wherein said digits C2, C3, C4, C5, C6, and C7 are the outputs of said adder.
Claim 3
Dependent Claim
139 words
A logic circuit for use in a 4 by 4 binary multiplier to produce the most significant bit of output therefrom, said circuit being responsive onLy to five logical variables (A3, B3, T4, L1 and X1) and comprising: a first level OR gate for forming the logical sum of said variable X1 with the negative of said variable L1; a first second level AND gate for forming the logical product of the output of said OR gate and said variable T4; a second second level AND gate for forming the logical product of said variable T4, said variable B3 and said variable A3; and a third level OR gate for forming the logical sum of the output of said first second level AND gate and the output of said second second level AND gate to form said variable C7.
Claim 4
Dependent Claim
139 words
A logic circuit for use in a 4 by 4 binary multiplier to produce the most significant bit of output therefrom, said circuit being responsive onLy to five logical variables (A3, B3, T4, L1 and X1) and comprising: a first level OR gate for forming the logical sum of said variable X1 with the negative of said variable L1; a first second level AND gate for forming the logical product of the output of said OR gate and said variable T4; a second second level AND gate for forming the logical product of said variable T4, said variable B3 and said variable A3; and a third level OR gate for forming the logical sum of the output of said first second level AND gate and the output of said second second level AND gate to form said variable C7.
Claim 5
Dependent Claim
208 words
An 8 by 8 bit multiplier for forming the product of a first 8-bit binary number N1 C + 16.A by a second 8-bit binary number N2 D + 16.B, said multiplier comprising: a first 4 by 4 bit binary multiplier for forming the product A.B; a second 4 by 4 bit multiplier for forming the product C.D; a third 4 by 4 bit multiplier for forming the product B.C; a fourth 4 by 4 bit multiplier for forming the product A.D; a first 8 by 8 bit adder responsive to the outputs of said third and fourth multipliers for forming the sum of said outputs as an 8 bit partial product as well as a first carry bit; a second 8 by 8 bit adder responsive to the four most significant bits output by said second multiplier and to the four least significant bits output from said first multiplier, as well as to said partial product, for forming the 5th through 12th bits of output and a second carry bit; and carry propagate logic means responsive to the four most significant bits of output from said first multiplier as well as to said first and said second carry bits for forming the 13th through 16th output bits.
Claim 6
Dependent Claim
208 words
An 8 by 8 bit multiplier for forming the product of a first 8-bit binary number N1 C + 16.A by a second 8-bit binary number N2 D + 16.B, said multiplier comprising: a first 4 by 4 bit binary multiplier for forming the product A.B; a second 4 by 4 bit multiplier for forming the product C.D; a third 4 by 4 bit multiplier for forming the product B.C; a fourth 4 by 4 bit multiplier for forming the product A.D; a first 8 by 8 bit adder responsive to the outputs of said third and fourth multipliers for forming the sum of said outputs as an 8 bit partial product as well as a first carry bit; a second 8 by 8 bit adder responsive to the four most significant bits output by said second multiplier and to the four least significant bits output from said first multiplier, as well as to said partial product, for forming the 5th through 12th bits of output and a second carry bit; and carry propagate logic means responsive to the four most significant bits of output from said first multiplier as well as to said first and said second carry bits for forming the 13th through 16th output bits.
Claim 7
Dependent Claim
93 words
The 8 by 8 bit multiplier of claim 3 wherein said carry propagate logic comprises a plurality of universal logic gates including but a single level of said gates responsive to said second carry bit, the output from any universal logic gate in a given level being independent of the output of any other such gate in said given level, whereby only one additional stage of propagation delay is introduced by said carry propagate logic in addition to those stages of propagation delay already required for the generation of said second carry bit.
Claim 8
Dependent Claim
347 words
A 4 by 4 bit multiplier for multiplying a first binary number A A0 +2. A1 + 4 A2 - 8.A3 by a second binary number B B0 + 2.B1 + 4.B2 - 8.B3 to form the 8-digit binary product C C0 + 2.C1 + 4.C2 + 8.C3 + 16.C4 + 32.C5 + 64C6 - 128.C7, said multiplier comprising: a first set of gating means for forming the individual digits of a binary number S (B0 + 2.B1) (A0 + 2.A1 + 4.A2 - 8.A3) S0 + 2.S1 + 4.S2 + 8.S3 + 16 .S4 - 32.S5; a second set of gating means for forming the variable T (B2 -2.B3) (A0 + 2.A1 + 4.A2 - 8.A3) T0 + 2.T1 + 4.T2 + 8.T3 -16.T5; and An adder comprising: first first-level gating means for forming a first intermediate variable X1 T1 + S3; second first-level gating means for forming a second intermediate variable X2 (T1 AND S3) OR ((T1 OR S3) AND S2 AND T0); third first-level gating means for forming an output digit C2 responsive to the S2 and T0 digits of said number S and T respectively; first second-level gating means responsive to said S digits and to said T digits as well as to said first intermediate variable X1 for forming said digit C3; second second-level gating means responsive to said S digits and to said T digits as well as to said second intermediate variable X2 for producing said digit C4; third second-level gating means for forming a third intermediate variable X3 T2 (S4 , T2 , X2), the right hand expression signifying a Threshold function True whenever two or more of its arguments are True, said third second-level gating means being responsive to said second intermediate variable X2 as well as to said digits T2 and S4; fourth second-level gating means for forming a fourth intermediate variable X4 T3 + S5; and wired gating means for forming the digit C5 X3 + X4 by the suitable cross connection of signals representative of variables X3 and X4 and their complements X3 and X4.
Claim 9
Dependent Claim
347 words
A 4 by 4 bit multiplier for multiplying a first binary number A A0 +2. A1 + 4 A2 - 8.A3 by a second binary number B B0 + 2.B1 + 4.B2 - 8.B3 to form the 8-digit binary product C C0 + 2.C1 + 4.C2 + 8.C3 + 16.C4 + 32.C5 + 64C6 - 128.C7, said multiplier comprising: a first set of gating means for forming the individual digits of a binary number S (B0 + 2.B1) (A0 + 2.A1 + 4.A2 - 8.A3) S0 + 2.S1 + 4.S2 + 8.S3 + 16 .S4 - 32.S5; a second set of gating means for forming the variable T (B2 -2.B3) (A0 + 2.A1 + 4.A2 - 8.A3) T0 + 2.T1 + 4.T2 + 8.T3 -16.T5; and An adder comprising: first first-level gating means for forming a first intermediate variable X1 T1 + S3; second first-level gating means for forming a second intermediate variable X2 (T1 AND S3) OR ((T1 OR S3) AND S2 AND T0); third first-level gating means for forming an output digit C2 responsive to the S2 and T0 digits of said number S and T respectively; first second-level gating means responsive to said S digits and to said T digits as well as to said first intermediate variable X1 for forming said digit C3; second second-level gating means responsive to said S digits and to said T digits as well as to said second intermediate variable X2 for producing said digit C4; third second-level gating means for forming a third intermediate variable X3 T2 (S4 , T2 , X2), the right hand expression signifying a Threshold function True whenever two or more of its arguments are True, said third second-level gating means being responsive to said second intermediate variable X2 as well as to said digits T2 and S4; fourth second-level gating means for forming a fourth intermediate variable X4 T3 + S5; and wired gating means for forming the digit C5 X3 + X4 by the suitable cross connection of signals representative of variables X3 and X4 and their complements X3 and X4.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-10-20 | 1979-04-21 | 1979-10-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-10-20 | 1983-04-21 | 1983-10-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-10-20 | 1987-04-21 | 1987-10-21 | $7700.00 | Window Closed / Lapsed |