Phase locked loop including an arithmetic unit

Claim 2

The combination comprising: 1 first means for providing a first digital signal representing a number N1; second means for providing a second digital signal representing a number N2; third means for providing a third digital signal having a reference frequency fR; fourth means for providing a fourth digital signal having a variable frequency fV; arithmetic means, including storage means for storing a digital sum signal representing the results of arithmetic operations, said arithmetic means being responsive to said first, second, third and fourth digital signals for adding said number N1 to the contents of said storage means at a frequency fR and subtracting said number N2 from the contents of said storage means at a frequency fV to thereby generate said sum signal; said fourth means further comprising a variable frequency means responsive to said sum signal for generating said fourth digital signal, said frequency fV of said fourth digital signal varying in accordance with the contents of said storage means; and output means coupled to said variable frequency means for generating an output signal having a frequency directly proportional to said frequency fV; the contents of said storage means remaining substantially constant when the total of the additions of N1 in a unit of time equals the total of the subtractions of N2 in said unit of time, said frequency fV being directly proportional to

Claim 3

The combination comprising: first means for providing a first digital signal representing a number N1; second means for providing a second digital signal representing a number N2; third means for providing a third digital signal having a reference frequency fR; fourth means for providing a fourth digital signal having a variable frequency fV; arithmetic means, including storage register means for storing a digital sum signal representing the results of arithmetic operations, said arithmetic means being responsive to said first, second, third and fourth digital signals for adding said number N1 to the contents of said storage register means at said frequency fR and subtracting said number N2 from the contents of said storage register means at said frequency fV to thereby generate said digital sum signal; digital to analogue converter means responsive to said digital sum signal for generating a DC control signal varying in accordance with said digital sum signal; said fourth means further comprising an oscillator means responsive to said DC control signal for generating said fourth digital signal, said frequency fV of said fourth digital signal varying in accordance with said DC signal; and oUtput means coupled to said oscillator means for generating an output AC signal having a frequency directly proportional to said frequency fV; the contents of said storage register means remaining substantially constant when the total of the additions of N1 in a unit of time equals the total of the subtractions of N2 in said unit of time, said frequency fV being directly proportional to

Claim 4

The combination comprising: first means for providing a first digital signal representing a number N1; second means for providing a second digital signal representing a number N2; third means for providing a third digital signal having a reference frequency fR; fourth means for providing a fourth digital signal having a variable frequency fV; arithmetic means, including storage register means for storing a digital sum signal representing the results of arithmetic operations, said arithmetic means being responsive to said first, second, third and fourth digital signals for adding said number N1 to the contents of said storage register means at said frequency fR and subtracting said number N2 from the contents of said storage register means at said frequency fV to thereby generate said digital sum signal; digital to analogue converter means responsive to said digital sum signal for generating a DC control signal varying in accordance with said digital sum signal; said fourth means further comprising an oscillator means responsive to said DC control signal for generating said fourth digital signal, said frequency fV of said fourth digital signal varying in accordance with said DC signal; and oUtput means coupled to said oscillator means for generating an output AC signal having a frequency directly proportional to said frequency fV; the contents of said storage register means remaining substantially constant when the total of the additions of N1 in a unit of time equals the total of the subtractions of N2 in said unit of time, said frequency fV being directly proportional to

Claim 5

The combination recited in claim 2 further including programming means for selectively changing the value of N1.

Claim 6

The combination recited in claim 3 further including programming means for selectively changing the value of N2.

Claim 7

The combination recited in claim 4 further including means for selecting controlling the value of N1 in response to a first control signal and controlling the value of N2 in response to a second control signal.

Claim 8

The combination recited in claim 5 wherein said first control signal periodically sweeps N1 between a first value and a second value, whereby the frequency fV is periodically swept between a first and a second frequency.

Claim 9

The combination recited in claim 5 wherein said output AC signal is frequencey modulated according to said first and second control signals.

Claim 10

The combination recited in claim 4, wherein said first digital signal, said second digital signal and said digital sum signal comprise rspective first, second and third groups of binary digits, said arithmetic means being arranged to simultaneously receive the binary digits in said first group and to simultaneously receive the binary digits in said second group, said storage register means being arranged to simultaneously store the binary digits in said third group, said arithmetic means being arranged to add said first group to the contents of said storage register means and to subtract said second group from the contents of said storage register means, said digital to analogue means being arranged to receive said third group of binary digits and to convert said third group to said DC control signal.

Claim 11

The combination recited in claim 8 including means to prevent additions of said number N1 from decreasing the value manifested by the contents of said storage register and to prevent subtractions of said number N2 from increasing the value manifested by the contents of said storage register.

Claim 12

The combination recited in claim 9, wherein said oscillator means includes an oscillator responsive to said Dc control signal to generate an oscillator output AC signal having a frequency KfV, wherein K is a predetermined number; a power splitter responsive to said oscillator output AC signal to couple a first portion of said oscillator output AC signal to said output means; said power splitter coupling a second portion of said oscillator output AC signal to a frequency divider, said frequency divider thereby dividing the frequency of said second portion of said oscillator output AC signal by said number K to thereby generate said fourth digital signal.

Claim 13

The combination recited in claim 8 wherein said frequency divider is a digital counter.

Claim 14

The combination recited in claim 11, wherein said oscillator is a voltage controlled oscillator and said digital to analogue converter means is adapted to generate a voltage varying in accordance to the contents of said output register means.

Claim 15

The combination recited in claim 11, wherein said digital to analogue converter means includes a digital to analogue converter coupled to said output register means to convert the contents of said output register into a pulse train having pulses whose amplitude varies in accordance with the contents of said output register means; and means responsive to said pUlse train for generating the average value of said pulse train to thereby form said DC control signal.

Claim 16

The combination recited in claim 13, wherein said means for averaging said pulse train includes an amplifier and a filter coupled in series, in the order named, between said digital to analogue converter and said oscillator.

Claim 17

The combination recited in claim 14, wherein said amplifier is an integrating amplifier arranged to integrate said pulse train.

Claim 18

The combination comprising: first means for providing a first digital signal representing a first number, second means for providing a second digital signal representing a second number; third means for providing a third digital signal having a first frequency; fourth means for providing a fourth digital signal having a second frequency, said second frequency being variable; arithmetic means, including storage means for storing a digital sum signal representing the results of arithmetic operations, said arithmetic means being responsive to said first, second, third and fourth digital signals for adding one of said numbers to the contents of said storage means at one of said first and second frequencies and for subtracting the other of said numbers from the contents of said storage means at the other of said first and second frequencies; and said fourth means further comprising a variable frequency means responsive to said sum signal for generating said fourth digital signal, said frequency of said fourth digital signal varying in accordance with the contents of said storage means.

Claim 19

The combination comprising: first means for providing a first digital signal representing a first number, second means for providing a second digital signal representing a second number; third means for providing a third digital signal having a first frequency; fourth means for providing a fourth digital signal having a second frequency, said second frequency being variable; arithmetic means, including storage means for storing a digital sum signal representing the results of arithmetic operations, said arithmetic means being responsive to said first, second, third and fourth digital signals for adding one of said numbers to the contents of said storage means at one of said first and second frequencies and for subtracting the other of said numbers from the contents of said storage means at the other of said first and second frequencies; and said fourth means further comprising a variable frequency means responsive to said sum signal for generating said fourth digital signal, said frequency of said fourth digital signal varying in accordance with the contents of said storage means.