Static control for step voltage regulator

Claim 2

In a control for a step voltage regulator adapted to raise and lower the regulator output voltage when raise and lower windings of a tap changer reversible electric motor are respectively energized, in combination, sensing means for deriving a sample voltage which is a function of the regulator output voltage, a predetermined reference voltage source, means for deriving upper and lower limit reference potentials which are respectively more positive and more negative than the reference voltage by a preselected fraction of said reference voltage and including bandwidth setting means for adjusting said preselected fraction, first and second comparator means for comparing said sample voltage respectively to said upper limit reference potential and to said lower limit reference potential, a timer adapted to provide an output a preselected time interval after it is started, first and second triggerable semiconductor switching means for respectively energizing said raise and lower motor windings, means for starting said timer in response to operation of said first comparator means or to operation of said comparator means, and first firing means for triggering said first semiconductor switching means in response to the simultaneous occurrence outputs from said timer and from said second comparator means, and second firing means for triggering said second semiconductor switching means in response to the simultaneous occurrence of outputs from said timer and from said first comparator means.

Claim 3

In a step regulator control in accordance with claim 1 wherein said bandwidth setting means includes a bandwidth setting potentiometer having its resistance element connected in a circuit across said reference voltage source and said lower limit reference potential is derived at the wiper of said potentiometer.

Claim 4

In a step regulator control in accordance with claim 2 wherein said means for deriving said upper limit reference potential includes a unity gain inverter amplifier having inputs coupled respectively to said reference voltage source and to said wiper of said bandwidth setting potentiometer.

Claim 5

In a step regulator control in accordance with claim 3 and including calibrating means for making said sample voltage equal to said reference voltage when the regulator output voltage is of the desired magnitude.

Claim 6

In a step regulator control in accordance with claim 4 wherein said timer includes a pulse generator for deriving a train of pulses at the frequency of the power line being regulated, a normally disabled digital counter receiving said train of pulses, digital-to-analog converting means for deriving a unidirectional timing voltage whose magnitude is proportional to the count stored in said counter, and comparator means for providing said timer output when said unidirectional timing voltage rises to the level of a predetermined reference potential, and wherein said means for starting said timer enables said digital counter.

Claim 7

In a step regulator control in accordance with claim 1 and including a latch between said comparator means and said firing means including cross-connected first and second logic gates which are respectively controlled by said first and second comparator means and whose outputs respectively control said second and first firing means.

Claim 8

In a step regulator control in accordance with claim 6 and including an oscillator for providing a train of high frequency triggering pulses for said semiconductor switching means, and wherein each of said first and second logic gates of said latch receive said timer output and said high frequency triggering pulses as inputs and is enabled when the timer, oscillator, and associated comparator means inputs thereto occur simUltaneously.

Claim 9

In a step regulator control in accordance with claim 1 wherein said timer includes a pulse generator for deriving a train of pulses at the frequency of the power line being regulated, a normally disabled digital counter receiving said train of pulses, digital-to-analog converting means for deriving a unidirectional timing voltage whose magnitude is porportional to the count stored in said counter, and comparator means for providing said timer output when said unidirectional timing voltage rises to the level of a predetermined reference potential, and wherein said means for starting said timer enables said digital counter.

Claim 10

In a control for a step voltage regulator having means to raise and lower the regulator output voltage when raise and lower windings of a reversible motor are respectively energized, sensing means for deriving a sample voltage which is a function of the regulator output voltage, a predetermined reference voltage source, means including a bandwidth setting potentiometer having its resistance element connected in a circuit across said reference voltage source for deriving a lower limit reference potential at the wiper of said potentiometer which is a preselected fraction of said reference voltage, lower limit comparator means for comparing said sample voltage to said lower limit reference potential, unity gain inverter means having inputs coupled to said potentiometer wiper and to said reference voltage source for deriving an upper limit reference potential which is greater than said reference voltage by the difference between said reference voltage and said lower limit reference potential, upper limit comparator means for comparing said sample voltage to said upper limit reference potential, first and second semiconductor switching means for respectively energizing said raise and lower motor windings, first firing means controlled by said upper limit comparator means for triggering said second semiconductor switching means, and second firing means controlled by said lower limit comparator means for triggering said first semiconductor switching means.

Claim 11

In a control for a step voltage regulator having means to raise and lower the regulator output voltage when raise and lower windings of a reversible motor are respectively energized, sensing means for deriving a sample voltage which is a function of the regulator output voltage, a predetermined reference voltage source, means including a bandwidth setting potentiometer having its resistance element connected in a circuit across said reference voltage source for deriving a lower limit reference potential at the wiper of said potentiometer which is a preselected fraction of said reference voltage, lower limit comparator means for comparing said sample voltage to said lower limit reference potential, unity gain inverter means having inputs coupled to said potentiometer wiper and to said reference voltage source for deriving an upper limit reference potential which is greater than said reference voltage by the difference between said reference voltage and said lower limit reference potential, upper limit comparator means for comparing said sample voltage to said upper limit reference potential, first and second semiconductor switching means for respectively energizing said raise and lower motor windings, first firing means controlled by said upper limit comparator means for triggering said second semiconductor switching means, and second firing means controlled by said lower limit comparator means for triggering said first semiconductor switching means.

Claim 12

In a control for a step voltage regulator having means to raise and lower the regulator output voltage when raise and lower windings of a reversible electric motor are respectively energized, sensing means for deriving a sample voltage which is proportional to the regulator output voltage, a predetermined reference voltage source, means including a bandwidth setting potentiometer for deriving a lower limit reference potential which is a preselected fraction of said reference voltage, means coupled to said reference voltage source and to the wiper of said bandwidth setting potentiometer for deriving an upper limit reference potential whose magnitude is equal to the sum of said reference voltage plus the difference between said reference voltage and said lower limit reference potential, first and second voltage comparator means for comparing said sample voltage respectively to said upper limit reference potential and to said lower limit reference potential, a timer adapted to be triggered into operation and to provide an output a preselected time interval after it is started, first and second triggerable semiconductor switching means for respectively energizing said raise and said lower motor windings, means for starting said timer in response to operation of said first voltage comparator means or to operation of said second voltage comparator means, first firing means for triggering said first semiconductor switching means in response to the simultaneous occurrence of outputs from said timer and from said second voltage comparator means, and second firing means for triggering said second semiconductor switching means in response to the simultaneous occurrence of outputs from said timer and from said first voltage comparator means.

Claim 13

In a control for a step voltage regulator having means to raise and lower the regulator output voltage when raise and lower windings of a reversible electric motor are respectively energized, sensing means for deriving a sample voltage which is proportional to the regulator output voltage, a predetermined reference voltage source, means including a bandwidth setting potentiometer for deriving a lower limit reference potential which is a preselected fraction of said reference voltage, means coupled to said reference voltage source and to the wiper of said bandwidth setting potentiometer for deriving an upper limit reference potential whose magnitude is equal to the sum of said reference voltage plus the difference between said reference voltage and said lower limit reference potential, first and second voltage comparator means for comparing said sample voltage respectively to said upper limit reference potential and to said lower limit reference potential, a timer adapted to be triggered into operation and to provide an output a preselected time interval after it is started, first and second triggerable semiconductor switching means for respectively energizing said raise and said lower motor windings, means for starting said timer in response to operation of said first voltage comparator means or to operation of said second voltage comparator means, first firing means for triggering said first semiconductor switching means in response to the simultaneous occurrence of outputs from said timer and from said second voltage comparator means, and second firing means for triggering said second semiconductor switching means in response to the simultaneous occurrence of outputs from said timer and from said first voltage comparator means.

Claim 14

In a control for a step voltage regulaTor having means to raise and means to lower the regulator output voltage, in combination, sensing means for deriving a D.C. sample voltage which is proportional to the regulator output voltage, a D.C. reference voltage source, means for deriving upper and lower limit reference potentials which are respectively more positive and more negative than the reference voltage by a fraction of said reference voltage and including bandwidth setting means for selectively adjusting said fraction, first and second voltage comparator means for comparing said sample voltage respectively to said upper limit reference potential and to said lower limit reference potential, pulse generator means for deriving a train of pulses at the frequency of the power line being regulated, a digital counter receiving said train of pulses from said pulse generator, means normally disabling said counter and being operated to enable said counter in response to an output from said first voltage comparator means or to an output from said second comparator means, digital-to-analog converting means for deriving a D.C. voltage whose magnitude is a function of the count stored in said counter, comparator means for providing a timer output when said D.C. voltage from said converting means rises to the level of a time delay establishing reference potential, means responsive to simultaneous outputs from said timer and said first voltage comparator means for actuating said means to lower the regulator output voltage, and means responsive to simultaneous outputs from said timer and said second voltage comparator means for actuating said means to raise the regulator output voltage.

Claim 15

In a control for a step voltage regulaTor having means to raise and means to lower the regulator output voltage, in combination, sensing means for deriving a D.C. sample voltage which is proportional to the regulator output voltage, a D.C. reference voltage source, means for deriving upper and lower limit reference potentials which are respectively more positive and more negative than the reference voltage by a fraction of said reference voltage and including bandwidth setting means for selectively adjusting said fraction, first and second voltage comparator means for comparing said sample voltage respectively to said upper limit reference potential and to said lower limit reference potential, pulse generator means for deriving a train of pulses at the frequency of the power line being regulated, a digital counter receiving said train of pulses from said pulse generator, means normally disabling said counter and being operated to enable said counter in response to an output from said first voltage comparator means or to an output from said second comparator means, digital-to-analog converting means for deriving a D.C. voltage whose magnitude is a function of the count stored in said counter, comparator means for providing a timer output when said D.C. voltage from said converting means rises to the level of a time delay establishing reference potential, means responsive to simultaneous outputs from said timer and said first voltage comparator means for actuating said means to lower the regulator output voltage, and means responsive to simultaneous outputs from said timer and said second voltage comparator means for actuating said means to raise the regulator output voltage.

Claim 16

In a control for a step voltage regulator having means to raise and lower the regulator output voltage when raise and lower windings of a reversible electric motor are respectively energized, sensing means for deriving a D.C. sample voltage which is a function of the regulator output voltage, a D.C. reference voltage source, means for deriving upper and lower limit reference potentials which are respectively more positive and more negative than the reference voltage by a preselected fraction of said reference voltage and including bandwidth setting means for adjusting said preselected fraction, first and second voltage comparator means for comparing said sample voltage respectively to said upper limit reference potential and to said lower limit reference potential, a pulse generator for deriving a train of pulses at the frequency of the power line being regulated, a digital source receiving said train of pulses from said pulse generator, means normally disabling said counter and being operated to enable said counter in response to an output from said first voltage comparator means or to an output from said voltage comparator means, digital-to-analog converting means for deriving a D.C. voltage whose magnitude is a function of the count stored in said counter, comparator means for providing a timer output when said D.C. voltage from said converting means rises to the level of a time delay establishing reference potential, first and second triggerable semiconductor switching means for respectively energizing said raise and lower motor windings, first firing circuit means for triggering said first semiconductor switching means in response to the simultaneous occurrence of an output from said second voltage comparator means and said timer output, and second firing circuit means for triggering said second semiconductor switching means in response to the simultaneous occurrence of said timer output and an output from said first voltage comparator means.

Claim 17

In a control for a step voltage regulator having means to raise and lower the regulator output voltage when raise and lower windings of a reversible electric motor are respectively energized, sensing means for deriving a D.C. sample voltage which is a function of the regulator output voltage, a D.C. reference voltage source, means for deriving upper and lower limit reference potentials which are respectively more positive and more negative than the reference voltage by a preselected fraction of said reference voltage and including bandwidth setting means for adjusting said preselected fraction, first and second voltage comparator means for comparing said sample voltage respectively to said upper limit reference potential and to said lower limit reference potential, a pulse generator for deriving a train of pulses at the frequency of the power line being regulated, a digital source receiving said train of pulses from said pulse generator, means normally disabling said counter and being operated to enable said counter in response to an output from said first voltage comparator means or to an output from said voltage comparator means, digital-to-analog converting means for deriving a D.C. voltage whose magnitude is a function of the count stored in said counter, comparator means for providing a timer output when said D.C. voltage from said converting means rises to the level of a time delay establishing reference potential, first and second triggerable semiconductor switching means for respectively energizing said raise and lower motor windings, first firing circuit means for triggering said first semiconductor switching means in response to the simultaneous occurrence of an output from said second voltage comparator means and said timer output, and second firing circuit means for triggering said second semiconductor switching means in response to the simultaneous occurrence of said timer output and an output from said first voltage comparator means.

Claim 18

In a control for a step voltage regulator adapted to raise and lower the regulator output voltage when raise and lower windings of a tap changer reversible electric motor are respectively energized, in combination, sensing means for deriving a D.C. sAmple voltage which is a function of the regulator output voltage, a D.C. reference voltage source, means for deriving upper and lower limit reference potentials which are respectively more positive and more negative than said reference voltage by a preselected portion of said reference voltage and including bandwidth setting means for adjusting said preselected portion, first and second voltage comparator means for comparing said sample voltage to said upper limit reference potential and to said lower limit reference potential respectively, a timer, means for starting said timer in response to operation of said first or of said second comparator means, a high frequency oscillator for providing a train of triggering pulses, first and second semiconductor switching means for respectively energizing said raise and lower motor windings, a latch comprising first and second logic gates which are respectively controlled by said first and second comparator means and are cross-connected so that only one logic gate at a time can be enabled, said first and second logic gates each receiving the output of said timer and the triggering pulses from oscillator as inputs and being respectively enabled when the timer, oscillator, and associated comparator means inputs thereto occur simultaneously, and first and second firing means responsive to the enabling of said first and of said second logic gates of said latch respectively for triggering said first and second semiconductor switching means.

Claim 19

In a control for a step voltage regulator adapted to raise and lower the regulator output voltage when raise and lower windings of a tap changer reversible electric motor are respectively energized, in combination, sensing means for deriving a D.C. sAmple voltage which is a function of the regulator output voltage, a D.C. reference voltage source, means for deriving upper and lower limit reference potentials which are respectively more positive and more negative than said reference voltage by a preselected portion of said reference voltage and including bandwidth setting means for adjusting said preselected portion, first and second voltage comparator means for comparing said sample voltage to said upper limit reference potential and to said lower limit reference potential respectively, a timer, means for starting said timer in response to operation of said first or of said second comparator means, a high frequency oscillator for providing a train of triggering pulses, first and second semiconductor switching means for respectively energizing said raise and lower motor windings, a latch comprising first and second logic gates which are respectively controlled by said first and second comparator means and are cross-connected so that only one logic gate at a time can be enabled, said first and second logic gates each receiving the output of said timer and the triggering pulses from oscillator as inputs and being respectively enabled when the timer, oscillator, and associated comparator means inputs thereto occur simultaneously, and first and second firing means responsive to the enabling of said first and of said second logic gates of said latch respectively for triggering said first and second semiconductor switching means.

Claim 20

In a control in accordance with claim 13 wherein said bandwidth setting means includes a bandwidth setting potentiometer having its resistance element connected in a circuit across said reference voltage source so that said lower limit reference potential is derived at the potentiometer wiper, and said means for deriving an upper limit reference potential includes a unity gain inverter operational amplifier having its inputs respectively coupled to said reference voltage source and to said wiper of said bandwidth setting potentiometer.

Claim 21

In a control in accordance with claim 13 wherein said timer includes a pulse generator for deriving a train of pulses at the frequency of the power line being regulated, a digital counter receiving said train of pulses, digital-to-analog converting means for deriving a D.C. timing voltage whose magnitude is proportional to the count stored in said counter, and comparator means for providing a timer output when said D.C. timing voltage rises to the level of a predetermined time delay establishing reference potential, said means for starting said timer normally disabling said digital counter and being adapted to enable said digital counter in response to operation of said first or of said second voltage comparator means.