US3725771A — Static control for step voltage regulator

Claim 1

Independent Claim 232 words

In a control for a step regulator having means to raise and lower the regulator output voltage when a raise signal and a lower signal respectively is applied thereto, in combination, a summing operational amplifier, sensing means for deriving a sample DC voltage which is a function of the regulator output voltage, said sensing means being coupled to one input of said summing amplifier, means for deriving a DC reference voltage of opposite polarity to said sample voltage, said reference voltage deriving means being coupled to said one input of said summing amplifier, whereby the output of said summing amplifier is zero when said sample and reference voltages are equal and is positive or negaTive dependent upon the relative magnitude of said sample and reference voltages, means responsive to the polarity of the output voltage from said summing amplifier and being operated when a preselected magnitude of input voltage is present on said one input of said summing amplifier for respectively deriving said raise and lower signals when said regulator output voltage is beyond the lower and upper bandwidth limits, and voltage bandwidth adjusting means for selectively varying the magnitude of said input voltage which must be applied to said one input of said summing amplifier to operate said raise and lower signal deriving means to thereby regulate the voltage bandwidth within which the output voltage of said step regulator is maintained.

Claim 2

Dependent Claim 232 words

In a control for a step regulator having means to raise and lower the regulator output voltage when a raise signal and a lower signal respectively is applied thereto, in combination, a summing operational amplifier, sensing means for deriving a sample DC voltage which is a function of the regulator output voltage, said sensing means being coupled to one input of said summing amplifier, means for deriving a DC reference voltage of opposite polarity to said sample voltage, said reference voltage deriving means being coupled to said one input of said summing amplifier, whereby the output of said summing amplifier is zero when said sample and reference voltages are equal and is positive or negaTive dependent upon the relative magnitude of said sample and reference voltages, means responsive to the polarity of the output voltage from said summing amplifier and being operated when a preselected magnitude of input voltage is present on said one input of said summing amplifier for respectively deriving said raise and lower signals when said regulator output voltage is beyond the lower and upper bandwidth limits, and voltage bandwidth adjusting means for selectively varying the magnitude of said input voltage which must be applied to said one input of said summing amplifier to operate said raise and lower signal deriving means to thereby regulate the voltage bandwidth within which the output voltage of said step regulator is maintained.

Claim 3

Dependent Claim 28 words

In a control for a step regulator in accordance with claim 1 wherein said voltage bandwidth adjusting means comprising means for adjusting the gain of said summing amplifier.

Claim 4

Dependent Claim 49 words

In the combination of claim 2 wherein said means for varying the gain of said summing amplifier includes a rheostat across which the output of said summing amplifier is applied and a resistance coupled between the contact arm of said rheostat and said one input of said summing amplifier.

Claim 5

Dependent Claim 54 words

In the bombination of claim 2 wherein said raise and lower signal deriving means includes a NPN and a PNP transistor having electrically commoned bases and a pair of serially arranged, oppositely poled zener diodes coupled between the output of said summing amplifier and the electrically commoned bases combination said NPN and PNP transistors.

Claim 6

Dependent Claim 119 words

In the combination of claim 4 wherein said one input of said summing amplifier is the inverting input and the noninverting input of said summing amplifier is coupled to ground and said raise and lower signal deriving means also includes first and second relays one of which has an operating coil in series with the emitter-collector circuit of said NPN transistor and the other of which has an operating coil in series with the emitter-collector circuit of said PNP transistor and first and second offset voltage circuit means each of which is completed by operation of one of said relays for applying a positive and a negative offset DC voltage respectively to said inverting input of said summing amplifier.

Claim 7

Dependent Claim 47 words

In the combination of claim 2 and including means actuated in response to operation of said raise and lower signal deriving means for respectively coupling DC offset voltages of opposite polarity to said one input of said summing amplifier when said raise and lower voltages are derived.

Claim 8

Dependent Claim 47 words

In the combination of claim 2 wherein said means for deriving a reference voltage includes a zener diode and said control includes series regulator means for deriving a regulated DC power supply and wherein said reference voltage zener diode is energized from said regulated DC power supply.

Claim 9

Dependent Claim 37 words

In the combination of claim 7 wherein said series regulator means includes a differential input second operational amplifier and the voltage across said reference voltage zener diode is coupled to one input of said second operational amplifier.

Claim 10

Dependent Claim 65 words

In the combination of claim 2 wherein said means for deriving a sample DC voltage includes a choke coil and said control also includes temperature compensation diode means positioned within said choke coil and coupled to said one input of said summing amplifier for compensating for changes in resistance of components of said control resulting from variations in temperature to which said control is subjected.

Claim 11

Dependent Claim 61 words

In the combination of claim 2 wherein said means for deriving a sample DC voltage includes a full wave rectifier bridge and said control also includes rectifier drop compensating diode means coupled to said one input of said summing amplifier for canceling variations in voltage drop across rectifiers of said bridge caused by temperature variations to which said control is subjected.

Claim 12

Dependent Claim 47 words

In the combination of claim 5 wherein said means for deriving raIse and lower signals also includes RC time delay means for providing a preselected time delay between the turning on of either of said transistors and the generation of the corresponding raise or said lower signal.

Claim 13

Dependent Claim 111 words

In the combination of claim 11 wherein said RC time delay means includes a differential input comparator operational amplifier, adjustable means including a time delay setting rheostat for applying a preselected voltage to one input of said comparator operational amplifier, a timing capacitor having one electrode coupled to the other input of said comparator operational amplifier, and means responsive to the turning on of either of said transistors for initiating charging of said timing capacitor in series with a resistance from a DC power supply, whereby the output of said comparator operational amplifier changes to the opposite polarity when the potential across said timing capacitor builds up to said preselected voltage.

Claim 14

Dependent Claim 81 words

In the combination of claim 12 wherein said means for deriving raise and lower signals also includes raise and lower relays, means responsive to the operation of one of said first and second relays and to said opposite polarity output of said comparator operational amplifier for energizing said raise relay, and means responsive to the operation of the other of said first and second relays and to said opposite polarity output of said comparator operational amplifier for energizing said lower relay.

Claim 15

Dependent Claim 22 words

In the combination of claim 12 wherein said summing operational amplifier and said comparator operational amplifier are of the integrated circuit type.

Claim 16

Dependent Claim 63 words

In the combination of claim 12 wherein said means for initiating charging of said timing capacitor includes a charging current transistor through which the charging current flows to said timing capacitor and means for biasing said charging current transistor in a direction to vary the magnitude of charging current flowing therethrough as a function of the voltage built up on said timing capacitor.

Claim 17

Dependent Claim 132 words

In the combination of claim 2 wherein said raise and lower signal deriving means includes first and second polarity and magnitude sensing means operable when the output voltage from said summing amplifier reaches a predetermined magnitude and is of positive and negative polarity respectively, an adjustable timer for providing a timer output signal a preselected time delay after it is triggered and being triggered upon operation of said first or said second polarity and magnitude sensing means, a first relay and a second relay, and means responsive to the operation of said first polarity and magnitude sensing means and said timer output signal for operating said first relay and being responsive to the operation of said second polarity and magnitude sensing means and said timer output signal for operating said second relay.

Claim 18

Dependent Claim 72 words

In the combination of claim 16 wherein said adjustable timer has an RC timing circuit including a timing capacitor, means for providing said timer output signal when the voltage across said timing capacitor builds up to a preselected potential, and time delay setting means for simultaneously adjusting both the magnitude of charging current to said timing capacitor and the potential across said timing capacitor at which said timer output signal is provided.

Claim 19

Dependent Claim 83 words

In the combination of claim 17 wherein said timer includes a differential input comparator operational amplifier, a charging current transistor connected in said RC charging circuit, means including a time setting rheostat for applying a preselected voltage to one input of said comparator amplifier, means for applying the voltage across said timing capacitor to the other input of said comparator amplifier, and biasing means for varying the charging current flowing through said transistor as a function of the voltage across said timing capacitor.

Claim 20

Dependent Claim 34 words

In the combination of claim 16 wherein said first and second polarity and magnitude sensing means includes a pair oF serially connected, oppositely poled zener diodes coupled to the output of said summing amplifier.

Claim 21

Dependent Claim 84 words

In the combination of claim 16 wherein said first polarity and magnitude sensing means includes a differential input second operational amplifier having its inverting input coupled to the output of said summing amplifier and also connected to a DC voltage source of predetermined positive potential, and said second polarity and magnitude sensing means includes a differential input third operational amplifier having its inverting input coupled to the output of said summing amplifier and also connected to a DC voltage source of predetermined negative potential.

Claim 22

Dependent Claim 109 words

In the combination of claim 20 wherein said means for operating said first relay includes a first NAND gate receiving said timer output signal on one input and having another input coupled to the output of said second operational amplifier and being connected to the cathode of a diode whose anode is grounded, and said means for operating said second relay includes a second NAND gate receiving said timer output signal on one input and having another input coupled through a NOT gate to the output of said third operational amplifier with the input to said NOT gate connected to the cathode of a diode whose anode is grounded.

Claim 23

Dependent Claim 42 words

In the combination of claim 16 and including means actuated in response to the operation of said first and second polarity and magnitude sensing means respectively for coupling DC offset voltages of opposite polarity to said one input of said summing amplifier.

Claim 24

Dependent Claim 202 words

In a control for a step voltage regulator having means to raise and lower the regulator output voltage when a raise and a lower signal respectively is applied thereto, in combination, sensing means for deriving a DC sample voltage which is a function of the regulator output voltage, means for deriving a DC reference voltage having a polarity opposite to said sample voltage, a summing operational amplifier having one input coupled to both said sensing means and to said reference signal deriving means, a NPN and PNP transistor, a pair of oppositely poled, series connected zener diodes coupled between the output of said summing amplifier and the bases of said NPN and PNP transistors, first and second relays each of which has an operating coil in series with the emitter-collector circuit of one of said transistors, offset voltage circuit means for applying DC offset voltages of opposite polarity to said one input of said summing amplifier in response to operation of said first and second relays respectively, and raise and lower signal generating circuit means including RC time delay means for deriving said raise and lower signals after a time delay in response to operation of said first and second relays respectively.

Claim 25

Dependent Claim 202 words

In a control for a step voltage regulator having means to raise and lower the regulator output voltage when a raise and a lower signal respectively is applied thereto, in combination, sensing means for deriving a DC sample voltage which is a function of the regulator output voltage, means for deriving a DC reference voltage having a polarity opposite to said sample voltage, a summing operational amplifier having one input coupled to both said sensing means and to said reference signal deriving means, a NPN and PNP transistor, a pair of oppositely poled, series connected zener diodes coupled between the output of said summing amplifier and the bases of said NPN and PNP transistors, first and second relays each of which has an operating coil in series with the emitter-collector circuit of one of said transistors, offset voltage circuit means for applying DC offset voltages of opposite polarity to said one input of said summing amplifier in response to operation of said first and second relays respectively, and raise and lower signal generating circuit means including RC time delay means for deriving said raise and lower signals after a time delay in response to operation of said first and second relays respectively.

Claim 26

Dependent Claim 34 words

In the combination of claim 23 and including means for selectively adjusting the gain of said summing operational amplifier to thereby regulate the bandwidth within which the output voltage of said regulator is maintained.

Claim 27

Dependent Claim 43 words

In the combination of claim 24 wherein said gain adjusting means includes a rheostat across which the output of said summing amplifier is applied and a resistance coupled between the contact arm of said rheostat and said one input of said summing amplifier.

Claim 28

Dependent Claim 102 words

In the combination of claim 23 wherein said RC time delay means includes a differential input second comparator operational amplifier, a timing capacitor coupled to one input of said comparator amplifier, means for applying a preselected DC voltage to the other input of said comparator amplifier, and means responsive to operation of said first or of said second relay for initiating charging of said timing capacitor in series with a resistance from a DC power source, whereby the output of said comparator amplifier changes to the opposite polarity when the potential across said timing capacitor builds up to said predetermined DC voltage.

Claim 29

Dependent Claim 90 words

In the combination of claim 26 wherein said means for initiating charging of said timing capacitor includes a charging current transistor in series with said resistance and said timing capacitor, said RC time delay means includes means for varying the bias on said charging current transistor as a function of the voltage across said timing capacitor, and said means for applying a preselected DC voltage to the other input of said comparator amplifier includes a time delay setting rheostat adapted to adjust said DC voltage applied to said other input.

Claim 30

Dependent Claim 52 words

In the combination of claim 27 and wherein said raise and lower signal generating means includes a raise relay and a lower relay and means responsive to both said opposite polarity output of said comparator amplifier and operation of said first and second relays respectively for energizing said raise and lower relays.

Claim 31

Dependent Claim 19 words

In the combination of claim 28 wherein said summing and comparator operational amplifiers are of the integrated circuit type.

Claim 32

Dependent Claim 70 words

In the combination of claim 23 wherein said means for deriving a DC reference voltage includes a reference voltage zener diode and said control also includes a series regulator including a diffeRential input second operational amplifier for deriving a regulated power supply, and wherein said reference voltage zener diode is energized from said regulated power supply and is also coupled to one input of said differential input second operational amplifier.

Claim 33

Dependent Claim 66 words

In the combination of claim 23 wherein said means for deriving a DC reference voltage includes a choke coil and said control also includes temperature compensation diode means positioned in said choke coil and coupled to said one input of said summing operational amplifier for compensating for changes in resistance of components of said control resulting from variations in temperature to which said control is subjected.

Claim 34

Dependent Claim 63 words

In the combination of claim 26 wherein said means for initiating charging of said timing capacitor includes a short circuiting transistor in shunt to said timing capacitor, means for normally biasing said short circuit transistor in the conductive state, and means responsive to the operation of said first or of said second relay for biasing said short circuiting transistor to the nonconductive state.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1976-04-02	1976-10-02	1977-04-03	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1980-04-02	1980-10-02	1981-04-03	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	1984-04-02	1984-10-02	1985-04-03	$7700.00	Window Closed / Lapsed

Static control for step voltage regulator

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