Integrated circuit for logic purposes having transistors with different base thicknesses and method of manufacturing

Claim 1

AN INTEGRATED CIRCUIT DEVICE COMPRISING: A. A SEMICONDUCTOR SUBSTRATE OF A FIRST CONDUCTIVITY TYPE B. A SURFACE LAYER OF A SECOND CONDUCTIVITY TYPE LOCATED ON SAID SUBSTRATE, C. ISOLATION DIFFUSION ZONES OF SAID FIRST CONDUCTIVITY TYPE EXTENDING FROM THE SURFACE OF SAID SURFACE LAYER INTO SAID SUBSTRATE, SAID ISOLATION DIFFUSION ZONES DIVIDING SAID SURFACE LAYER INTO A PLURALITY OF ISLANDS, D. AT LEAST ONE MULTI-EMITTER TRANSISTOR OF ONE TYPE LOCATED INDIVIDUALLY WITHIN ONE OF SAID ISLANDS AND COMPRISING A COLLECTOR REGION AND A BASE REGION, E. AT LEAST ONE FURTHER TRANSISTOR OF SAID ONE TYPE LOCATED INDIVIDUALLY WITHIN ANOTHER ONE OF SAID ISLANDS, SAID FURTHER TRANSISTOR INCLUDING A BASE REGION ELECTRICALLY CONNECTED TO SAID COLLECTOR REGION OF SAID MULTI-EMITTER TRANSISTOR, SAID BASE REGION OF SAID MULTI-EMITTER TRANSISTOR SIGNIFICANTLY EXCEEDING IN THICKNESS SAID BASE REGION OF SAID FURTHER TRANSISTOR, AND F. LOCAL BURIED LAYERS OF SAD SECOND CONDUCTIVITY TYPE LOCATED IN AT LEAST SAID ONE AND SAID OTHER ISLANDS AT THE INTERFACE BETWEEN SAID SUBSTRATE AND SAID SURFACE LAYER, SAID BURIED LAYERS HAVING DIMENSIONS WITHIN THE BOUNDARIES OF THEIR RESPECTIVE SAID ISLANDS, SAID MULTI-EMITTER AND SAID FURTHER TRANSISTORS BEING DISPOSED ABOVE THEIR RESPECTIVE SAID BURIED LAYERS, SAID BASE REGION OF SAID MULTI-EMITTER TRANSISTOR EXTENDING FROM SAID SURFACE INTO ITS ASSOCIATED BURIED LAYER TO A GREATER DEPTH THAN SAID BASE REGION OF SAID FURTHER TRANSISSTOR AND CONSTITUTING WITH ITS ASSOCIATED BURIED LAYER PART OF THE COLLECTOR JUNCTION OF SAID MULTI-EMITTER TRANSISTOR, SAID BASE REGION OF SAID FURTHER TRANSISTOR BEING SPACED FROM ITS ASSOCIATED BURIED LAYER.