Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
262 words
A digital telecommunications switching system comprising: a series of switching stages, a plurality of input channels connected to a first stage of said series of switching stages, a plurality of output channels connected to the last stage of said series of switching stages, control means connected to each of said switching stages for effecting a communication path through the switching stages, each switching stage comprising a switching memory containing a plurality of data words, each said data word containing an address determining an outlet from said stage, each said switching stage further comprising means for reading said data words cyclically, and decoding means for selecting an outlet from the switching stage in dependence upon the address contained in a data word currently being read out, each data word of a said plurality of data words in one of the stages of said switching memory containing, in addition to said address, a first data field controlling the operation of said decoding means and a second data field providing an indication to said control means of whether said associated outlet is free for the establishment of a said communication path thereto, said control means including means for writing into a selected said first field data preventing the operation of said decoding means, and consequent completion of a communication path to the associated outlet, and into the associated said second field data representing said associated outlet as busy, and means for over-writing the data in said first field and consequently enabling said decoding means and the completion of said communication path to said associated outlet.
Claim 2
Dependent Claim
262 words
A digital telecommunications switching system comprising: a series of switching stages, a plurality of input channels connected to a first stage of said series of switching stages, a plurality of output channels connected to the last stage of said series of switching stages, control means connected to each of said switching stages for effecting a communication path through the switching stages, each switching stage comprising a switching memory containing a plurality of data words, each said data word containing an address determining an outlet from said stage, each said switching stage further comprising means for reading said data words cyclically, and decoding means for selecting an outlet from the switching stage in dependence upon the address contained in a data word currently being read out, each data word of a said plurality of data words in one of the stages of said switching memory containing, in addition to said address, a first data field controlling the operation of said decoding means and a second data field providing an indication to said control means of whether said associated outlet is free for the establishment of a said communication path thereto, said control means including means for writing into a selected said first field data preventing the operation of said decoding means, and consequent completion of a communication path to the associated outlet, and into the associated said second field data representing said associated outlet as busy, and means for over-writing the data in said first field and consequently enabling said decoding means and the completion of said communication path to said associated outlet.
Claim 3
Dependent Claim
58 words
A switching system according to claim 1, wherein said first field contains a single ''''busy'''' bit which enables or disables said decoding means according to the value of the busy bit, and said second field contains a single ''''reserve'''' bit which indicates that the associated outlet is busy or free according to the value of the reserve bit.
Claim 4
Dependent Claim
80 words
A switching system according to claim 2, wherein said one switching stage is the last of said switching stages and comprises a time-division switching circuit for receiving a time-division mulitplexed signal containing data from a plurality of said input channels time-division multiplexed together in respective time slots, there being a said data word stored in said switching memory and cycled in correspondence with said time slots in respect of each output channel for which an input channel signal is intended.
Claim 5
Dependent Claim
29 words
A switching system according to claim 3, wherein said series of switching stages comprises a time-division switching stage, a space-division switching stage and a time-division switching stage in sequence.