Method and device for control of the transmission of data exchanged between a control processor and a plurality of peripheral devices

Claim 1

A method of control of transmission of data exchanged between a central processor and at least one peripheral unit through a transmission channel, said method comprising: sending a cycle of signals in two sequences, said sequences comprising: sending a first data transmission demand sequence comprising information relative to the direction of the transmission and the addressing of the data to be transmitted; and sending a second data transmission sequence; wherein said first data transmission demand sequence comprises: sending a so-called outwards transfer signal from the central processor to the peripheral unit, said outwards transfer signal fixing the direction of the data exchange; sending a so-called outwards check signal, while positioning information concerning the addressing of the data at an input to said channel by the central processor; detecting the appearance of the outwards check signal and sending a so-called inwards check signal to the central processor; detecting the inwards check signal and causing the outwards check signal to relapse; detecting the relapse of the outwards check signal; transmitting said address to the peripheral unit through said transmission channel; effecting a check of said address information; causing the inwards check signal to relapse; and detecting the relapse of the inwards check signal whereby the cycle can recommence.

Claim 2

A method of control of transmission of data exchanged between a central processor and at least one peripheral unit through a transmission channel, said method comprising: sending a cycle of signals in two sequences, said sequences comprising: sending a first data transmission demand sequence comprising information relative to the direction of the transmission and the addressing of the data to be transmitted; and sending a second data transmission sequence; wherein said first data transmission demand sequence comprises: sending a so-called outwards transfer signal from the central processor to the peripheral unit, said outwards transfer signal fixing the direction of the data exchange; sending a so-called outwards check signal, while positioning information concerning the addressing of the data at an input to said channel by the central processor; detecting the appearance of the outwards check signal and sending a so-called inwards check signal to the central processor; detecting the inwards check signal and causing the outwards check signal to relapse; detecting the relapse of the outwards check signal; transmitting said address to the peripheral unit through said transmission channel; effecting a check of said address information; causing the inwards check signal to relapse; and detecting the relapse of the inwards check signal whereby the cycle can recommence.

Claim 6

A method of control of transmission of data exchanged between a central processor and at least one peripheral unit through a transmission channel, said method comprising: sending a cycle of signals in two sequences, said sequences comprising: sending a first data transmission demand sequence comprising information relative to the direction of the transmission and the addressing of the data to be transmitted; and sending a second data transmission sequence; wherein said second data transmission sequence for a so-called outwards or write exchange direction from the central processor to the peripheral unit comprises: detecting the fall of a so-called inwards check signal at the end of the first data sequence, positioning the data to be transmitted to the peripheral unit at an input to the channel while generating a so-called outwards sampling signal; detecting the appearance of the outwards sampling signal and generating a so-called inwards sampling signal; detecting the appearance of the inwards sampling signal and causing the outwards sampling signal to relapse; detecting the relapse of the outwards sampling signal; effecting a check of the data and recording the data at the address in the peripheral unit specified during the first sequence; causing the inwards sampling signal to relapse and causing a so-called inwards transfer signal to appear; detecting the appearance of the inwards transfer signal and causing a so-called outwards transfer signal to fall; detecting the fall of the outwards transfer signal and causing the inwards transfer signal to relapse; and detecting the relapse of the inwards transfer signal which causes the outward transfer signal to reappear whereby a new cycle can be undertaken.

Claim 7

A method of control of transmission of data exchanged between a central processor and at least one peripheral unit through a transmission channel, said method comprising: sending a cycle of signals in two sequences, said sequences comprising: sending a first data transmission demand sequence comprising information relative to the direction of the transmission and the addressing of the data to be transmitted; and sending a second data transmission sequence; wherein said second data transmission sequence for a so-called outwards or write exchange direction from the central processor to the peripheral unit comprises: detecting the fall of a so-called inwards check signal at the end of the first data sequence, positioning the data to be transmitted to the peripheral unit at an input to the channel while generating a so-called outwards sampling signal; detecting the appearance of the outwards sampling signal and generating a so-called inwards sampling signal; detecting the appearance of the inwards sampling signal and causing the outwards sampling signal to relapse; detecting the relapse of the outwards sampling signal; effecting a check of the data and recording the data at the address in the peripheral unit specified during the first sequence; causing the inwards sampling signal to relapse and causing a so-called inwards transfer signal to appear; detecting the appearance of the inwards transfer signal and causing a so-called outwards transfer signal to fall; detecting the fall of the outwards transfer signal and causing the inwards transfer signal to relapse; and detecting the relapse of the inwards transfer signal which causes the outward transfer signal to reappear whereby a new cycle can be undertaken.

Claim 10

A method of control of transmission of data exchanged between a central processor and at least one peripheral unit through a transmission channel, said method comprising: sending a cycle of signals in two sequences, said sequences comprising: sending a first data transmission demand sequence comprising information relative to the direction of the transmission and the addressing of the data to be transmitted; and sending a second data transmission sequence; wherein said second data transmission sequence for a so-called inwards or read exchange direction from the peripheral unit to the central processor comprises: detecting the fall of a so-called inwards check signal; positioning the data to be transferred from the address in the peripheral unit defined during the first sequence at an input to the channel; causing a so-called inwards transfer signal to appear causing a so-called outwards transfer signal to fall; detecting the fall of the outwards transfer signal and causing a so-called inwards sampling signal to appear; detecting the appearance of the inwards sampling signal and causing a so-called outwards sampling signal to appear; detecting the appearance of the outwards sampling signal and causing the inwards sampling signal to relapse; detecting the relapse of the inwards sampling signal; recording the data in the central processor and causing the outwards sampling signal to relapse; and detecting the relapse of the outwards sampling signal which causes the inwards transfer signal to relapse and the outwards transfer signal to reappear whereby a new cycle can be undertaken.

Claim 11

A method of control of transmission of data exchanged between a central processor and at least one peripheral unit through a transmission channel, said method comprising: sending a cycle of signals in two sequences, said sequences comprising: sending a first data transmission demand sequence comprising information relative to the direction of the transmission and the addressing of the data to be transmitted; and sending a second data transmission sequence; wherein said second data transmission sequence for a so-called inwards or read exchange direction from the peripheral unit to the central processor comprises: detecting the fall of a so-called inwards check signal; positioning the data to be transferred from the address in the peripheral unit defined during the first sequence at an input to the channel; causing a so-called inwards transfer signal to appear causing a so-called outwards transfer signal to fall; detecting the fall of the outwards transfer signal and causing a so-called inwards sampling signal to appear; detecting the appearance of the inwards sampling signal and causing a so-called outwards sampling signal to appear; detecting the appearance of the outwards sampling signal and causing the inwards sampling signal to relapse; detecting the relapse of the inwards sampling signal; recording the data in the central processor and causing the outwards sampling signal to relapse; and detecting the relapse of the outwards sampling signal which causes the inwards transfer signal to relapse and the outwards transfer signal to reappear whereby a new cycle can be undertaken.

Claim 13

A device for control of transmission of data between a central processor and at least one peripheral unit through a transmission channel, said device comprising: a first data transmission control circuit connected to said central processor, said first circuit including a first emitter and a first receiver; a second data transmission control circuit connected to a peripheral unit, said second circuit including a second emitter and a second receiver; said first emitter coupled to said second receiver for sending control signals to said second receiver in a so-called outwards or write direction, said second emitter coupled to said first receiver for sending control signals to said first receiver in a so-called inwards or read direction, said first and second circuits cooperating so as to exchange a cycle of data transmission control signals comprising: a first sequence comprising information relative to the direction of the transmission and the addressing of the data to be transmitted, and a second sequence of transmission of these data through said transmission channel; first means for checking data transmitted in said write direction and for signaling said second emitter to send to said first receiver an error signal which causes an initialization of said cycle of control signals; and second means responsive to said second emitter for enabling the passage of the information or the data through said channel; wherein said emitters and receivers cooperate to exchange signals during said first sequence said cooperation comprising: said first emitter sends a so-called outwards transfer signal to said second receiver during the whole of said first sequence, while the second emitter keeps a so-called inwards transfer siGnal at a low level during the whole of said first sequence, said transfer signals for fixing the direction of the exchange; said first emitter generates a so-called outwards check signal, while the information concerning the addressing of the data is positioned at an input to said channel; said second receiver detects the appearance of the outwards check signal and causes said second emitter to generate a so-called inwards check signal; said first receiver detects the appearance of the inwards check signal and causes said first emitter to let the outwards check signal relapse; said second receiver detects the relapse of the outwards check signal and signals said second means to enable the passage of data, whereby the addressing information is received by the peripheral unit while the first means simultaneously checks the information; the second emitter causes the inwards check signal to relapse, and said first receiver detects the relapse of the inwards check signal whereby the cycle can recommence.

Claim 14

A device for control of transmission of data between a central processor and at least one peripheral unit through a transmission channel, said device comprising: a first data transmission control circuit connected to said central processor, said first circuit including a first emitter and a first receiver; a second data transmission control circuit connected to a peripheral unit, said second circuit including a second emitter and a second receiver; said first emitter coupled to said second receiver for sending control signals to said second receiver in a so-called outwards or write direction, said second emitter coupled to said first receiver for sending control signals to said first receiver in a so-called inwards or read direction, said first and second circuits cooperating so as to exchange a cycle of data transmission control signals comprising: a first sequence comprising information relative to the direction of the transmission and the addressing of the data to be transmitted, and a second sequence of transmission of these data through said transmission channel; first means for checking data transmitted in said write direction and for signaling said second emitter to send to said first receiver an error signal which causes an initialization of said cycle of control signals; and second means responsive to said second emitter for enabling the passage of the information or the data through said channel; wherein said emitters and receivers cooperate to exchange signals during said first sequence said cooperation comprising: said first emitter sends a so-called outwards transfer signal to said second receiver during the whole of said first sequence, while the second emitter keeps a so-called inwards transfer siGnal at a low level during the whole of said first sequence, said transfer signals for fixing the direction of the exchange; said first emitter generates a so-called outwards check signal, while the information concerning the addressing of the data is positioned at an input to said channel; said second receiver detects the appearance of the outwards check signal and causes said second emitter to generate a so-called inwards check signal; said first receiver detects the appearance of the inwards check signal and causes said first emitter to let the outwards check signal relapse; said second receiver detects the relapse of the outwards check signal and signals said second means to enable the passage of data, whereby the addressing information is received by the peripheral unit while the first means simultaneously checks the information; the second emitter causes the inwards check signal to relapse, and said first receiver detects the relapse of the inwards check signal whereby the cycle can recommence.

Claim 17

A device for control of transmission of data between a central processor and at least one peripheral unit through a transmission channel, said device comprising: a first data transmission control circuit connected to said central processor, said first circuit including a first emitter and a first receiver; a second data transmission control circuit connected to a peripheral unit, said second circuit including a second emitter and a second receiver; said first emitter coupled to said second receiver for sending control signals to said second receiver in a so-called outwards or write direction, said second emitter coupled to said first receiver for sending control signals to said first receiver in a so-called inwards or read direction, said first and second circuits cooperating so as to exchange a cycle of data transmission control signals comprising: a first sequence comprising information relative to the direction of the transmission and the addressing of the data to be transmitted, and a second sequence of transmission of these data through said transmission channel; first means for checking data transmitted in said write direction and for signaling said second emitter to send to said first receiver an error signal which causes an initialization of said cycle of control signals; and second means responsive to said second emitter for enabling the passage of the information or the data through said channel; wherein said emitter and said receivers cooperate to exchange signals during said second sequence in a direction of data exchange known as the outwards or write directions, said cooperation comprising: the first receiver detecting the fall of a so-called inwards check signal at the end of the first sequence; said first receiver causing said first emitter to generate a so-called outwards sampling signal while the data to be transferred is positioned at an input to the channel; said second receiver detects the appearance of the outwards sampling signal and causing the second emitter to generate a so-called inwards sampling signal; said first receiver detects the appearance of the inwards sampling signal and causing the first emitter to let the outwards sampling signal relapse; said second receiver detects the relapse of the outwards sampling signal and signals the second means to enable the passage of data, whereby the data are simultaneously recorded by the peripheral unit while the first means check said data; said second emitter causes the inwards sampling signal to relapse and a so-called inwards transfer signal to appear; said first receiver detects the relapse of the inwards sampling signal and causes the first emitter to let a so-called outwards transfer signal fall; said second receiver detects the fall of the outwards transfer signal and causes the second emitter to let the inwards transfer signal relapse; said first receiver detects the relapse of the inwards transfer signal and causes the first emitter to make the outward transfer signal reappear whereby a new cycle can be undertaken.

Claim 18

A device for control of transmission of data between a central processor and at least one peripheral unit through a transmission channel, said device comprising: a first data transmission control circuit connected to said central processor, said first circuit including a first emitter and a first receiver; a second data transmission control circuit connected to a peripheral unit, said second circuit including a second emitter and a second receiver; said first emitter coupled to said second receiver for sending control signals to said second receiver in a so-called outwards or write direction, said second emitter coupled to said first receiver for sending control signals to said first receiver in a so-called inwards or read direction, said first and second circuits cooperating so as to exchange a cycle of data transmission control signals comprising: a first sequence comprising information relative to the direction of the transmission and the addressing of the data to be transmitted, and a second sequence of transmission of these data through said transmission channel; first means for checking data transmitted in said write direction and for signaling said second emitter to send to said first receiver an error signal which causes an initialization of said cycle of control signals; and second means responsive to said second emitter for enabling the passage of the information or the data through said channel; wherein said emitter and said receivers cooperate to exchange signals during said second sequence in a direction of data exchange known as the outwards or write directions, said cooperation comprising: the first receiver detecting the fall of a so-called inwards check signal at the end of the first sequence; said first receiver causing said first emitter to generate a so-called outwards sampling signal while the data to be transferred is positioned at an input to the channel; said second receiver detects the appearance of the outwards sampling signal and causing the second emitter to generate a so-called inwards sampling signal; said first receiver detects the appearance of the inwards sampling signal and causing the first emitter to let the outwards sampling signal relapse; said second receiver detects the relapse of the outwards sampling signal and signals the second means to enable the passage of data, whereby the data are simultaneously recorded by the peripheral unit while the first means check said data; said second emitter causes the inwards sampling signal to relapse and a so-called inwards transfer signal to appear; said first receiver detects the relapse of the inwards sampling signal and causes the first emitter to let a so-called outwards transfer signal fall; said second receiver detects the fall of the outwards transfer signal and causes the second emitter to let the inwards transfer signal relapse; said first receiver detects the relapse of the inwards transfer signal and causes the first emitter to make the outward transfer signal reappear whereby a new cycle can be undertaken.

Claim 19

A device for control of transmission of data between a central processor and at least one peripheral unit through a transmission channel, said device comprising: a first data transmission control circuit connected to said central processor, said first circuit including a first emitter and a first receiver; a second data transmission control circuit connected to a peripheral unit, said second circuit including a second emitter and a second receiver; said first emitter coupled to said second receiver for sending control signals to said second receiver in a so-called outwards or write direction, said second emitter coupled to said first receiver for sending control signals to said first receiver in a so-called inwards or read direction, said first and second circuits cooperating so as to exchange a cycle of data transmission control signals comprising: a first sequence comprising information relative to the direction of the transmission and the addressing of the data to be transmitted, and a second sequence of transmission of these data through said transmission channel; first means for checking data transmitted in said write direction and for signaling said second emitter to send to said first receiver an error signal which causes an initialization of said cycle of control signals; and second means responsive to said second emitter for enabling the passage of the information or the data through said channel; wherein said emitters and said receivers cooperate to exchange signals during said second sequence for a direction of transmission known as the inwards or read direction, said cooperation comprising: said first receiver detects the fall of a so-called inwards check signal and causes the first emitter to let a so-called outwards transfer signal fall; said second receiver detects the fall of the outwards transfer signal and causes the second emitter to make a so-called inwards transfer signal appear, and a so-Called inwards sampling signal appear while the data to be transferred is positioned at an input to said channel; said first receiver detects the appearance of the inwards sampling signal and causes the first emitter to make a so-called outwards sampling signal appear; said second receiver detects the appearance of the outwards sampling signal and causes the second emitter to let the inwards sampling signal relapse; said first receiver detects the relapse of the inwards sampling signal and causes the first emitter to let the outwards sampling signal relapse, while the second means enables the passage of data whereby the data are recorded by the central processor; said second receiver detects the relapse of the outwards sampling signal and causes the second emitter to let the inwards transfer signal relapse; said first receiver detects the relapse of the inwards transfer signal and causes the first emitter to make the outwards transfer signal reappear, whereby a new cycle can be undertaken.

Claim 20

A device for control of transmission of data between a central processor and at least one peripheral unit through a transmission channel, said device comprising: a first data transmission control circuit connected to said central processor, said first circuit including a first emitter and a first receiver; a second data transmission control circuit connected to a peripheral unit, said second circuit including a second emitter and a second receiver; said first emitter coupled to said second receiver for sending control signals to said second receiver in a so-called outwards or write direction, said second emitter coupled to said first receiver for sending control signals to said first receiver in a so-called inwards or read direction, said first and second circuits cooperating so as to exchange a cycle of data transmission control signals comprising: a first sequence comprising information relative to the direction of the transmission and the addressing of the data to be transmitted, and a second sequence of transmission of these data through said transmission channel; first means for checking data transmitted in said write direction and for signaling said second emitter to send to said first receiver an error signal which causes an initialization of said cycle of control signals; and second means responsive to said second emitter for enabling the passage of the information or the data through said channel; wherein said emitters and said receivers cooperate to exchange signals during said second sequence for a direction of transmission known as the inwards or read direction, said cooperation comprising: said first receiver detects the fall of a so-called inwards check signal and causes the first emitter to let a so-called outwards transfer signal fall; said second receiver detects the fall of the outwards transfer signal and causes the second emitter to make a so-called inwards transfer signal appear, and a so-Called inwards sampling signal appear while the data to be transferred is positioned at an input to said channel; said first receiver detects the appearance of the inwards sampling signal and causes the first emitter to make a so-called outwards sampling signal appear; said second receiver detects the appearance of the outwards sampling signal and causes the second emitter to let the inwards sampling signal relapse; said first receiver detects the relapse of the inwards sampling signal and causes the first emitter to let the outwards sampling signal relapse, while the second means enables the passage of data whereby the data are recorded by the central processor; said second receiver detects the relapse of the outwards sampling signal and causes the second emitter to let the inwards transfer signal relapse; said first receiver detects the relapse of the inwards transfer signal and causes the first emitter to make the outwards transfer signal reappear, whereby a new cycle can be undertaken.