Patent US3909724A successfully refreshed from Google Patents.
US3909724A
Expired / Lapsed
US
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Start bit detector and data strober for asynchronous receiver
Assignee: AB Dick Co
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Filing: 1973-06-26
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Granted: 1975-09-30
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Expires: 1993-06-26
Abstract
Abstract An asynchronous data receiver is provided comprising a start bit detector which samples the received data at a clock rate which is a multiple of the data bit rate and analyzes a plurality of consecutive samples to distinguish an actual start bit from noise spikes, or the like. When receipt of an actual start bit has been confirmed, a bit rate clock source is started by the detector at mid-bit position of the start bit, whereby each of the data bits of a character is strobed at mid-bit time.
Inventors
- 👤 James J Spoth
- 👤 Robert J Robbins
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 23:15
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/02; H04L25/06; H04L25/068
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
122 words
A character start bit detector for an asynchronous receiver which receives digital data of predetermined bit rate, said detector comprising: clock generator means for providing clock signals at a clock rate which is a predetermined multiple of said bit rate, memory means for storing sample signals representative of the received digital data at said clock rate, means for decoding said sample signals stored in said memory means and providing a start bit detection signal in response to a predetermined consecutive number of said stored sample signals being of the same logic level and at least one of said stored sample signals being of the opposite logic level, and means for inhibiting said decoding means in response to said start bit detection signal.
Claim 2
Dependent Claim
122 words
A character start bit detector for an asynchronous receiver which receives digital data of predetermined bit rate, said detector comprising: clock generator means for providing clock signals at a clock rate which is a predetermined multiple of said bit rate, memory means for storing sample signals representative of the received digital data at said clock rate, means for decoding said sample signals stored in said memory means and providing a start bit detection signal in response to a predetermined consecutive number of said stored sample signals being of the same logic level and at least one of said stored sample signals being of the opposite logic level, and means for inhibiting said decoding means in response to said start bit detection signal.
Claim 3
Dependent Claim
136 words
A character start bit detector for an asynchronous receiver which receives digital data of predetermined bit rate, said detector comprising: clock generator means for providing clock signals at a clock rate which is a predetermined multiple of said bit rate, memory means for storing sample signals representative of the reCeived digital data at said clock rate, and means for decoding said sample signals stored in said memory means and providing a start bit detection signal in response to a predetermined consecutive number of said stored sample signals being of the same logic level and at least one of said stored sample signals being of the opposite logic level, said predetermined number of sample signals corresponding in time to approximately one half of the bit time, whereby said start bit detection signal occurs near mid bit time.
Claim 4
Dependent Claim
136 words
A character start bit detector for an asynchronous receiver which receives digital data of predetermined bit rate, said detector comprising: clock generator means for providing clock signals at a clock rate which is a predetermined multiple of said bit rate, memory means for storing sample signals representative of the reCeived digital data at said clock rate, and means for decoding said sample signals stored in said memory means and providing a start bit detection signal in response to a predetermined consecutive number of said stored sample signals being of the same logic level and at least one of said stored sample signals being of the opposite logic level, said predetermined number of sample signals corresponding in time to approximately one half of the bit time, whereby said start bit detection signal occurs near mid bit time.
Claim 5
Dependent Claim
170 words
A character start bit detector for an asynchronous receiver which receives digital data of predetermined bit rate, said detector comprising: clock generator means for providing clock signals at a clock rate which is a predetermined multiple of said bit rate, memory means for storing sample signals representative of the received digital data at said clock rate, means for decoding said sample signals stored in said memory means and providing a start bit detection signal in response to a predetermined consecutive number of said stored sample signals being of the same logic level and at least one of said stored sample signals being of the opposite logic level, and bit rate counter means enabled in response to the occurrence of said start bit detection signal for providing a count representative of the number of data bits following a character start bit, said stored sample signal of opposite logic level being the logic level of the input data immediately prior to a transition at the leading edge of a character start bit.
Claim 6
Dependent Claim
170 words
A character start bit detector for an asynchronous receiver which receives digital data of predetermined bit rate, said detector comprising: clock generator means for providing clock signals at a clock rate which is a predetermined multiple of said bit rate, memory means for storing sample signals representative of the received digital data at said clock rate, means for decoding said sample signals stored in said memory means and providing a start bit detection signal in response to a predetermined consecutive number of said stored sample signals being of the same logic level and at least one of said stored sample signals being of the opposite logic level, and bit rate counter means enabled in response to the occurrence of said start bit detection signal for providing a count representative of the number of data bits following a character start bit, said stored sample signal of opposite logic level being the logic level of the input data immediately prior to a transition at the leading edge of a character start bit.
Claim 7
Dependent Claim
121 words
For use with an asynchronous receiver which receives digital data characters at a predetermined bit rate, a start bit detector comprising: first means for sampling the received digital data and providing a first logic signal upon detection of a character start bit, said first logic signal occurring in time near the center of said start bit; second means responsive to said first logic signal to provide a second logic signal for inhibiting said first means; and bit rate pulse generating means enabled by said second logic signal to initiate generation of pulses at the center of said detected start bit whereby a pulse occurs at the center of each succeeding bit of the character to control strobing at mid bit position.
Claim 8
Dependent Claim
121 words
For use with an asynchronous receiver which receives digital data characters at a predetermined bit rate, a start bit detector comprising: first means for sampling the received digital data and providing a first logic signal upon detection of a character start bit, said first logic signal occurring in time near the center of said start bit; second means responsive to said first logic signal to provide a second logic signal for inhibiting said first means; and bit rate pulse generating means enabled by said second logic signal to initiate generation of pulses at the center of said detected start bit whereby a pulse occurs at the center of each succeeding bit of the character to control strobing at mid bit position.
Claim 9
Dependent Claim
53 words
The receiver set forth in claim 4 including counter means for counting the number of said pulses subsequent to detection of a character start bit, said counter means initiating count in response to said second logic signal and enabling said first means upon reaching a predetermined count corresponding to a predetermined bit count.
Claim 10
Dependent Claim
28 words
The receiver set forth in claim 4 wherein said first means samples the received data at a clock rate which is a predetermined multiple of said bit rate.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-09-29 | 1979-03-31 | 1979-09-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-09-29 | 1983-03-31 | 1983-09-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-09-29 | 1987-03-31 | 1987-09-30 | $7700.00 | Window Closed / Lapsed |