Abstract There is provided a frequency measuring circuit in which a plurality of counters having the same counting period are connected in parallel with an input terminal, and the time of beginning of counting by the counters is sequentially delayed a predetermined time from that of the preceeding counter, whereby when each counter completes its counting, a register sequentially stores the counted value in place of the previously stored one. In this way, even when the counting period of the individual counters is increased to obtain an improved measuring accuracy, the data interval between one data and the succeeding one can be reduced and thus the frequency measuring circuit of this invention operates with greatly improved response characteristic and accuracy.
Inventors
👤 Yoshiaki Nakano
Bibliographic Details
Application Number—
JurisdictionUS
Data Sourcegoogle_patents
Last Synchronized2026-10-25 15:35
CPC Classifications
G; G01; G01R; G01R23/00; G01R23/02
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
141 words
A frequency measuring circuit comprising an input terminal, a plurality of counters each having an input connected in parallel to said input terminal for simultaneously receiving the same portions of a train of pulses to be counted and an output terminal and each having the same counting period, register means connected to the output terminals of each of said counters to store, upon receipt of a storage signal, the count thereof, and circuit means connected to said counters for sequentially delaying the beginning of the counting of each of said counters a predetermined time beyond the beginning of counting of the preceding counter and connected to said register means for producing said storage signal to cause storage in said register of the count of each of said counters upon completion of the counting thereof at the end of said counting period.
Claim 2
Dependent Claim
141 words
A frequency measuring circuit comprising an input terminal, a plurality of counters each having an input connected in parallel to said input terminal for simultaneously receiving the same portions of a train of pulses to be counted and an output terminal and each having the same counting period, register means connected to the output terminals of each of said counters to store, upon receipt of a storage signal, the count thereof, and circuit means connected to said counters for sequentially delaying the beginning of the counting of each of said counters a predetermined time beyond the beginning of counting of the preceding counter and connected to said register means for producing said storage signal to cause storage in said register of the count of each of said counters upon completion of the counting thereof at the end of said counting period.
Claim 3
Dependent Claim
25 words
A frequency measuring circuit according to claim 1, wherein said register means includes gate means connected between each of said counters and said register means.
Claim 4
Dependent Claim
52 words
A frequency measuring circuit according to claim 2, wherein said circuit means comprises a reference signal generator, a dividing counter connected to said reference signal generator to divide the frequency of the reference signal therefrom, and a decoder connected to said frequency dividing counter to generate control signals including said storage signal.