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US3909700A Expired / Lapsed US ⏱️ 0.0 years remaining

Monolithic semiconductor rectifier circuit structure

Assignee: General Electric Co
•
Filing: 1974-01-18
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Granted: 1975-09-30
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Expires: 1994-01-18
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Abstract

Abstract A monolithic semiconductor rectifier circuit structure incorporating two npn power transistors and two Schottky-barrier diodes is disclosed. The transistors are connected in an inverted mode and are the main rectifying elements. The Schottky-barrier diodes are connected between the emitters and collectors of the respective transistors and help to initiate rapid turn-on of the transistors. The Schottky-barrier diodes have a relatively low forward voltage drop and their reverse recovery currents are substantially zero. Thus, the Schottky diodes operate with minimum power loss. The monolithic circuit structure may be combined with a discrete current transformer unit to form a hybrid rectifying circuit.

Inventors

  • 👤 Armand P Ferro

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-26 19:25
CPC Classifications
H; H02; H02M; H02M7/00; H02M7/02; H02M7/04; H02M7/12; H02M7/21; H02M7/217; H02M7/2173; H10; H10D; H10D84/00; H10D84/60; H10D84/611; H10D84/613; H10D84/617

Claims Analysis

Total Claims: 3
Claim 1
Independent Claim 659 words
A hybrid circuit, suitable for being electrically connected between a power transformer including a secondary winding with a grounded center-tap terminal between two end terminals of said secondary winding and a load including a first terminal and a grounded second terminal, for converting an alternating voltage existing across said secondary winding to d.c. and supplying d.c. to said load, said hybrid circuit comprising: a discrete multiwinding current control transformer unit in combination with a monolithic semiconductor structure; said transformer unit comprising a magnetic core member on which a first primary winding, a first secondary winding, a secondary primary winding and a second secondary winding are wound and magnetically coupled, each of the aforesaid primary and secondary windings having one and other ends, said one ends of the first primary and the first secondary windings having opposite winding polarities and being electrically connected and defining a first input terminal of the hybrid circuit, said one ends of the second primary and the second secondary windings having winding polarities opposite to each other as well as opposite to the corresponding one ends of the first primary and the first secondary windings, said one ends of the second primary and second secondary windings being electrically connected and defining a second input terminal of the hybrid circuit; said monolithic, semiconductor circuit structure comprising an n doped substrate having first and second back-to-back surfaces, an n doped layer epitaxially grown on said first surface of the substrate, said n doped layer having a surface in back-to-back relation with said first surface of the substrate on which the layer is grown, first and second p doped regions diffused in and laterally spaced along said layer and extending from the surface of said layer into said layer toward, but not meeting, the substrate, first and second n doped regions, each being diffused into a different one of the first and second p doped regions and extending from the surface of the p doped region into said p doped region toward, but not meeting, the interface between the p doped region and the n doped layer, each n doped region encompassed, except at the surface thereof, by the p doped region in which it is diffused, first and second laterally spaced metallization regions deposited on and intimately bonded to said surface of the n doped layer and forming thereat first and second metal-semiconductor junctions, said first and second metallization regions comprising anodes of first and second Schottky-barrier diodes, respectively, said first aNd second n doped regions comprising emitters of first and second npn transistors, respectively, said first and second p doped regions comprising bases of said first and second npn transistors, respectively, said second surface of said n doped substrate comprising common collectors of said first and second npn transistors as well as common cathodes of said first and second Schottky-barrier diodes, first means electrically connecting said surface of said first n doped region and said first metallization region, second means electrically connecting said surface of said second n doped region and said second metallization region, said first means being electrically connected to said other end of said first primary winding, said second means being electrically connected to said other end of said second primary winding, third means electrically connecting said first p doped region to said other end of said first secondary winding, and fourth means electrically connecting said second p doped region to said other end of said second secondary winding, said second surface of said n doped substrate defining a first output terminal of the hybrid circuit, said hybrid circuit being connectable between the power transformer and the load such that the first and second input terminals of the hybrid circuit are connectable to the end terminals, respectively, of the secondary winding of the power transformer and the second surface of the n doped substrate defining the first output terminal of the hybrid circuit is electrically connected to said first terminal of the load.
Claim 2
Dependent Claim 659 words
A hybrid circuit, suitable for being electrically connected between a power transformer including a secondary winding with a grounded center-tap terminal between two end terminals of said secondary winding and a load including a first terminal and a grounded second terminal, for converting an alternating voltage existing across said secondary winding to d.c. and supplying d.c. to said load, said hybrid circuit comprising: a discrete multiwinding current control transformer unit in combination with a monolithic semiconductor structure; said transformer unit comprising a magnetic core member on which a first primary winding, a first secondary winding, a secondary primary winding and a second secondary winding are wound and magnetically coupled, each of the aforesaid primary and secondary windings having one and other ends, said one ends of the first primary and the first secondary windings having opposite winding polarities and being electrically connected and defining a first input terminal of the hybrid circuit, said one ends of the second primary and the second secondary windings having winding polarities opposite to each other as well as opposite to the corresponding one ends of the first primary and the first secondary windings, said one ends of the second primary and second secondary windings being electrically connected and defining a second input terminal of the hybrid circuit; said monolithic, semiconductor circuit structure comprising an n doped substrate having first and second back-to-back surfaces, an n doped layer epitaxially grown on said first surface of the substrate, said n doped layer having a surface in back-to-back relation with said first surface of the substrate on which the layer is grown, first and second p doped regions diffused in and laterally spaced along said layer and extending from the surface of said layer into said layer toward, but not meeting, the substrate, first and second n doped regions, each being diffused into a different one of the first and second p doped regions and extending from the surface of the p doped region into said p doped region toward, but not meeting, the interface between the p doped region and the n doped layer, each n doped region encompassed, except at the surface thereof, by the p doped region in which it is diffused, first and second laterally spaced metallization regions deposited on and intimately bonded to said surface of the n doped layer and forming thereat first and second metal-semiconductor junctions, said first and second metallization regions comprising anodes of first and second Schottky-barrier diodes, respectively, said first aNd second n doped regions comprising emitters of first and second npn transistors, respectively, said first and second p doped regions comprising bases of said first and second npn transistors, respectively, said second surface of said n doped substrate comprising common collectors of said first and second npn transistors as well as common cathodes of said first and second Schottky-barrier diodes, first means electrically connecting said surface of said first n doped region and said first metallization region, second means electrically connecting said surface of said second n doped region and said second metallization region, said first means being electrically connected to said other end of said first primary winding, said second means being electrically connected to said other end of said second primary winding, third means electrically connecting said first p doped region to said other end of said first secondary winding, and fourth means electrically connecting said second p doped region to said other end of said second secondary winding, said second surface of said n doped substrate defining a first output terminal of the hybrid circuit, said hybrid circuit being connectable between the power transformer and the load such that the first and second input terminals of the hybrid circuit are connectable to the end terminals, respectively, of the secondary winding of the power transformer and the second surface of the n doped substrate defining the first output terminal of the hybrid circuit is electrically connected to said first terminal of the load.
Claim 3
Dependent Claim 112 words
The hybrid integrated circuit set forth in claim 1 wherein said monolithic semiconductor circuit structure is further comprised of an additional n doped region diffused into said n doped layer beginning at the surface thereof and extending into said n doped layer toward, but not meeting, the surface of the substrate on which said n doped layer is epitaxially grown, said additional n doped region being arranged and distributed in said n doped layer so as to individually surround each of said first and second p doped regions and form n isolation diffusions between said p doped regions as well as an n doped isolation diffusion surrounding both said p doped regions.

References Cited (Backward Citations)

US3379940A Cited
US3649883A Cited
US3737742A Cited
US3795846A Cited
US3735235A Cited
US3751726A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1978-09-29 1979-03-31 1979-09-30 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1982-09-29 1983-03-31 1983-09-30 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1986-09-29 1987-03-31 1987-09-30 $7700.00 Window Closed / Lapsed

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