US3909635A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Cycling timer apparatus with automatic interruption and hold
Assignee: Nikon Corp
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Filing: 1973-12-26
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Granted: 1975-09-30
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Expires: 1993-12-26
Abstract
Abstract Timers for controlling load circuits, such as motors in motordriven cameras, have ON and OFF intervals which can either be continuously repeated or automatically interrupted after various selected sequences of ON-OFF operations for thereafter holding the load circuit in an energized or de-energized state. The timers comprise a bi-stable circuit having complementary output signals and a pair of CR time-delay circuits for generating timedelayed signals in response to the output signals, the timedelayed signals being coupled to respective inputs of the bistable circuit for causing the bi-stable circuit to be alternately set in first and second states. A load responsive to one of the output signals is energized or de-energized in accordance with the state of the bi-stable circuit. An interrupter circuit responsive to one of the time-delayed signals causes the load to be continuously energized or de-energized after a selected ON-OFF sequence.
Inventors
- 👤 Osamu Maida
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 11:56
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/28; G; G03; G03B; G03B17/00; G03B17/42; G03B17/425; G03B19/00; G03B19/18; H03K3/00; H03K3/02; H03K3/027; H03K3/03; H03K3/26; H03K3/28; H03K3/281; H03K3/282; H03K3/2823; H03K3/64
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
163 words
A cycling timer with automatic interruption and hold comprising: bistable means having first and second inputs for setting said bistable means to first and second states, respectively, said bistable means providing at respective output terminals first and second complementary signals in accordance with the state of said bistable means, first time delay means responsive to said first signal for generating a time-delayed third signal, second time delay means responsive to said second signal for generating a time-delayed fourth signal, means for coupling said third and fourth signals to said first and second inputs, respectively, of said bistable means whereby said bistable means is cycled between said first and second states, load control means connected to said bistable means and having different states responsive to the states of said bistable means, and hold means connected to said bi-stable means for causing said load control means to maintain a state thereof continuously after a predetermined time interval determined by the operation of said bistable means.
Claim 2
Dependent Claim
163 words
A cycling timer with automatic interruption and hold comprising: bistable means having first and second inputs for setting said bistable means to first and second states, respectively, said bistable means providing at respective output terminals first and second complementary signals in accordance with the state of said bistable means, first time delay means responsive to said first signal for generating a time-delayed third signal, second time delay means responsive to said second signal for generating a time-delayed fourth signal, means for coupling said third and fourth signals to said first and second inputs, respectively, of said bistable means whereby said bistable means is cycled between said first and second states, load control means connected to said bistable means and having different states responsive to the states of said bistable means, and hold means connected to said bi-stable means for causing said load control means to maintain a state thereof continuously after a predetermined time interval determined by the operation of said bistable means.
Claim 3
Dependent Claim
60 words
A timer as set forth in claim 1, wherein each of said delay means comprises integrating means, means responsive to the associated one of said first and second signals for setting the initial state of said integrating means, and threshold detecting means responsive to the associated one of said integrating means for producing one of said third and fourth signals.
Claim 4
Dependent Claim
17 words
A timer as set forth in claim 1, further comprising switch means for disablinG said hold means.
Claim 5
Dependent Claim
48 words
A timer as set forth in claim 1, wherein said timer has start means for initiating operation of said load control timer, and means connected to said bistable means and said start means for selectively setting said bistable means to either one of said first and second states.
Claim 6
Dependent Claim
55 words
A timer as set forth in claim 1, wherein said hold means comprises memory means having set and reset states, and wherein said memory means is connected to one of said time delay means and is switched from said reset state to said set state in response to one of said third and fourth signals.
Claim 7
Dependent Claim
24 words
A load timer as set forth in claim 5, wherein said memory means comprises a pair of transistors having electrodes interconnected for positive feedback.
Claim 8
Dependent Claim
16 words
A timer as set forth in claim 5, wherein said memory means comprises a controlled rectifier.
Claim 9
Dependent Claim
28 words
A timer as set forth in claim 1, wherein said hold means comprises means having an output connected to said load control means independent of said bistable means
Claim 10
Dependent Claim
37 words
A timer as set forth in claim 8, wherein said hold means comprises means connected to said second time delay means for preventing said fourth signal from being applied to said second input of said bistable means.
Claim 11
Dependent Claim
37 words
A timer as set forth in claim 9, wherein said means for preventing said fourth signal from being applied to said second input comprises means for preventing said second time delay means from producing said fourth signal.
Claim 12
Dependent Claim
68 words
A timer as set forth in claim 10, wherein said second time delay means comprises integrating means, means responsive to said second signal for setting said integrating means in an initial state during one state of said bistable means and for permitting said integrating means to integrate during the other state of said bistable means, and trigger means responsive to said integrating means for producing said fourth signal.
Claim 13
Dependent Claim
34 words
A timer as set forth in claim 11, wherein said means for preventing said second time delay means from producing said fourth signal comprises means connected to said trigger means for disabling the same.
Claim 14
Dependent Claim
37 words
A time as set forth in claim 11, wherein said means for preventing said second time delay means from producing said fourth signal comprises means connected to said integrating means for preventing integration by that integrating means.
Claim 15
Dependent Claim
26 words
A timer as set forth in claim 13, wherein said means for preventing integration comprises means for maintaining the last-mentioned integrating means in said initial state.
Claim 16
Dependent Claim
36 words
A timer as set forth in claim 13, wherein the last-mentioned integrating means comprises a series-connected resistor and capacitor, and wherein said means for preventing integration comprises transistor means connected to said capacitor for short-circuiting it.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-09-29 | 1979-03-31 | 1979-09-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-09-29 | 1983-03-31 | 1983-09-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-09-29 | 1987-03-31 | 1987-09-30 | $7700.00 | Window Closed / Lapsed |