US3611204A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Wide pulse low prf pulse generator
Assignee: United States Department of the Air Force
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Filing: 1969-03-20
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Granted: 1971-10-05
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Expires: 1989-03-20
Abstract
Abstract A pulse generator capable of producing wide low RPF pulses having fast rise and fall times is realized by circuits which alternately drive a bistable device. A multivibrator is periodically placed in a first stable state by a unijunction transistor relaxation oscillator having a slow period of oscillation. The multivibrator is returned to its second stable state by a unijunction transistor circuit that is activated by the first stable state voltage condition of the multivibrator. A time delay circuit associated with the unijunction transistor circuit delays actuation of the unijunction transistor and thus establishes the pulse width of the pulse generator.
Inventors
- 👤 Robert A Boenning
- 👤 Robert W Mcniel
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 19:53
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/35; H03K3/351; H03K3/78
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
333 words
A wide pulse, low-pulse repetition frequency pulse generator comprising, a supply voltage source, a bistable multivibrator circuit having first and second transistors, first and second pulse generator output terminals, first and second emitter follower transistors, the collector of said first multivibrator transistor being connected through resistance means to said supply voltage source and to the base of said first emitter follower transistor, and the collector of said second multivibrator transistor being connected through resistance means to said supply voltage source and to the base of said second emitter follower transistor, the emitter of said first emitter follower transistor being connected to said first pulse generator output terminal and the emitter of said second emitter follower transistor being connected to said second pulse generator output terminal, a trigger pulse generator for generating trigger pulses at a desired pulse generator pulse repetition frequency comprising a relaxation oscillator utilizing a unijunction transistor and including a capacitor resistance circuit having a time delay characteristic equal to the pulse generator pulse period, said capacitance resistance circuit being connected between one base of said unijunction transistor, ground, and the base of said first multivibrator transistor, the other base of said unijunction transistor being connected through resistance means to said supply voltage source, the emitter of said unijunction transistor being connected through capacitance means to ground and through resistance means to said supply voltage source, and, a monostable circuit having a time delay characteristic equal to the desired pulse generator pulse width, said monostable circuit comprising a relaxation oscillator utilizing a unijunction transistor, the emitter of said monostable circuit unijunction transistor being connected through resistance means to the emitter of said second emitter follower transistor and through capacitance means to ground, a first base of said monostaBle circuit unijunction transistor being connected through a capacitor-resistance circuit to ground and to the base of said second multivibrator transistor, the other base of said monostable circuit unijunction transistor being connected through resistance means to the collector of said first emitter follower transistor.
Claim 2
Dependent Claim
333 words
A wide pulse, low-pulse repetition frequency pulse generator comprising, a supply voltage source, a bistable multivibrator circuit having first and second transistors, first and second pulse generator output terminals, first and second emitter follower transistors, the collector of said first multivibrator transistor being connected through resistance means to said supply voltage source and to the base of said first emitter follower transistor, and the collector of said second multivibrator transistor being connected through resistance means to said supply voltage source and to the base of said second emitter follower transistor, the emitter of said first emitter follower transistor being connected to said first pulse generator output terminal and the emitter of said second emitter follower transistor being connected to said second pulse generator output terminal, a trigger pulse generator for generating trigger pulses at a desired pulse generator pulse repetition frequency comprising a relaxation oscillator utilizing a unijunction transistor and including a capacitor resistance circuit having a time delay characteristic equal to the pulse generator pulse period, said capacitance resistance circuit being connected between one base of said unijunction transistor, ground, and the base of said first multivibrator transistor, the other base of said unijunction transistor being connected through resistance means to said supply voltage source, the emitter of said unijunction transistor being connected through capacitance means to ground and through resistance means to said supply voltage source, and, a monostable circuit having a time delay characteristic equal to the desired pulse generator pulse width, said monostable circuit comprising a relaxation oscillator utilizing a unijunction transistor, the emitter of said monostable circuit unijunction transistor being connected through resistance means to the emitter of said second emitter follower transistor and through capacitance means to ground, a first base of said monostaBle circuit unijunction transistor being connected through a capacitor-resistance circuit to ground and to the base of said second multivibrator transistor, the other base of said monostable circuit unijunction transistor being connected through resistance means to the collector of said first emitter follower transistor.
References Cited (Backward Citations)
US3125730A
Cited
US2997665A
Cited
US3259854A
Cited
US3349255A
Cited
US3388346A
Cited
US3497725A
Cited
US3465174A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-10-04 | 1975-04-05 | 1975-10-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-10-04 | 1979-04-05 | 1979-10-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-10-04 | 1983-04-05 | 1983-10-05 | $7700.00 | Window Closed / Lapsed |