US3909630A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High-rate integration, squelch and phase measurements
Assignee: International Business Machines Corp
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Filing: 1974-01-23
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Granted: 1975-09-30
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Expires: 1994-01-23
Abstract
Abstract An H-configured integration circuit includes a pair of squelch transistors forming two legs of the H with a pair of integrating switch transistors forming the other two legs. A pair of capacitors having a common terminal to a reference potential form the crossbar in the H. Rapid integration and differentially balanced squelching is provided for both capacitors. A phase shift measuring circuit shares the squelch reference with the integration circuit such that any variation in the reference on the integrator also adjusts the phase shift measuring circuit. Such circuit differentially compares the integrated values from the integrators with a reference derived from the squelch for indicating phase shift of the input integrated signal with respect to a timing reference.
Inventors
- 👤 Benjamin C Fiorino
- 👤 Peter T Marino
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 01:14
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/02; H04L25/06
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
193 words
Signal processing apparatus, including in combination: first and second electrical signal storage capacitors having a common terminal at a reference potential and each having a signal terminal; first and second current source transistor elements having commonly connected base electrodes and commonly connected collector electrodes for connection to a power signal source, said first and second current source transistor elements having emitter electrodes respectively ohmically connected to said signal terminals of said first and second signal storage capacitors; first and second current sink transistor elements having collector electrodes respectively ohmically connected to said first and second signal terminals, commonly ohmically connected emitter electrodes, and electrically independent base electrodes; means for receiving input signals having a given periodicity to be processed and supplying such received signals to said independent base electrodes; timing signal generator means responsive to said received signals to generate a timing signal indicative of said given periodicity; first and second constant current sinks; and first switching means responsive to said periodicity indication to alternately and successively connect said first and second constant current sinks to said commonly connected emitter electrodes and to said emitter electrodes of said current source transistor elements, respectively.
Claim 2
Dependent Claim
193 words
Signal processing apparatus, including in combination: first and second electrical signal storage capacitors having a common terminal at a reference potential and each having a signal terminal; first and second current source transistor elements having commonly connected base electrodes and commonly connected collector electrodes for connection to a power signal source, said first and second current source transistor elements having emitter electrodes respectively ohmically connected to said signal terminals of said first and second signal storage capacitors; first and second current sink transistor elements having collector electrodes respectively ohmically connected to said first and second signal terminals, commonly ohmically connected emitter electrodes, and electrically independent base electrodes; means for receiving input signals having a given periodicity to be processed and supplying such received signals to said independent base electrodes; timing signal generator means responsive to said received signals to generate a timing signal indicative of said given periodicity; first and second constant current sinks; and first switching means responsive to said periodicity indication to alternately and successively connect said first and second constant current sinks to said commonly connected emitter electrodes and to said emitter electrodes of said current source transistor elements, respectively.
Claim 3
Dependent Claim
71 words
Apparatus as set forth in claim 1 wherein said first and second current source transistor elements have matched electrical characteristics; squelch reference means connected to said commonly connected base electrodes; and an output circuit connected to said electrical signal storage capacitor signal terminals and having a circuit portion thereof electrically connected to said squelch reference means for processing signals received from said signal terminals in accordance with said squelch reference means.
Claim 4
Dependent Claim
193 words
Alternately cycled integration apparatus consisting of first and second signal processing apparatus set forth in claim 1, the improvement further including in combination: first and second integration timing transistor elements in said first switching means having commonly connected emitter electrodes and collector electrodes respectively connected to said commonly connected emitter electrodes of said first and second current sink transistor elements, respectively, in said first and second signal processing apparatus; said first current sink connected to said commonly connected emitter electrodes of said integration timing transistor elements; said timing signal generator means supplying + and - timing signals as said periodicity indication; a base electrode in each said integration timing transistor element respectively receiving said + and - timing signals to alternately and successively actuate said first and second signal processing apparatus to integrating operations; and squelch control means in said first switching means responsive to said + and - timing signals to alternately and successively actuate said first and second current source transistor elements, respectively, in said second and first signal processing apparatus such that when one of said signal processing apparatus is integrating another of said signal processing apparatus is being squelched.
Claim 5
Dependent Claim
143 words
Alternately cycled integration apparatus set forth in claim 3, wherein said squelch control means further includes a switching transistor element having an emitter electrode; third reference means biasing said switching transistor element to a reference threshold for becoming current conductive; first and second squelch sink transistor elements in each said signal processing apparatus with collector electrodes connected to said signal terminals in said signal processing apparatus, resPectively, commonly connected base electrodes connected to said third reference means and each said squelch sink transistor elements having emitter electrodes connected to said emitter electrode of said switching transistor element; and first and second switching control elements interposed between said third reference means and said commonly connected base electrodes of said squelch sink transistor elements in said first and second signal processing apparatus and respectively responsive to said - and + timing signals to actuate same.
Claim 6
Dependent Claim
70 words
Alternately cycled integration apparatus set forth in claim 4 further including in combination: a signal level translation means connected to said squelch reference means and having a level output terminal supplying a fourth reference signal related to said squelch reference signal; and a signal output circuit connected to said signal terminals and to said level output terminal to supply output signals indicative of integrated signals in said signal storage capacitors.
Claim 7
Dependent Claim
57 words
Alternately cycled integration apparatus set forth in claim 5 wherein said signal output circuit includes a timing transistor element responsive to said timing signal generator means to time operation of said signal output circuit with said periodicity indication; and another current sink in said signal output circuit exhibiting environmental variation characteristics similar to said second current sink.
Claim 8
Dependent Claim
70 words
Alternately cycled integration apparatus set forth in claim 6 wherein said signal output apparatus further includes: a comparator circuit portion with a given comparison threshold having one input connected to a first given one of said signal terminals and a second input connected to said level output terminal; and said another current sink connected to said second input such that said given comparison threshold varies with said squelch reference signal.
Claim 9
Dependent Claim
153 words
Alternately cycled integration apparatus set forth in claim 7 wherein said comparator circuit has a third input connected to a second given one of said signal terminals, said first and second given one signal terminals being in one of said signal processing apparatus; first, second, and third compare transistor elements having commonly connected emitter electrodes and base electrodes respectively connected to said first, second, and third inputs, collector electrodes in said first and third compare transistor elements being connected together, a collector electrode on said second compare transistor element; and a compare latch timed by said timing signal generator means and having first and second inputs respectively connected to collector electrodes of said first and second compare transistor elements and having an output terminal for carrying a signal indicating phase error when both said first and second compare transistor elements are current nonconductive at a time indicated by said timing signal generator means.
Claim 10
Dependent Claim
96 words
A signal processing circuit having first and second portions for repetitively serially processing input signals therethrough, said first portion processing signals then supplying first processed signals to said second portion for processing, the improvement including in combination: first reference means in said first portion supplying a first reference signal for establishing a given quiescent signal state in said first portion when it is not processing signals; and second reference means in said second portion responsive to said first reference to establish an operational reference in said second portion for processing signals received from said first portion.
Claim 11
Dependent Claim
96 words
A signal processing circuit having first and second portions for repetitively serially processing input signals therethrough, said first portion processing signals then supplying first processed signals to said second portion for processing, the improvement including in combination: first reference means in said first portion supplying a first reference signal for establishing a given quiescent signal state in said first portion when it is not processing signals; and second reference means in said second portion responsive to said first reference to establish an operational reference in said second portion for processing signals received from said first portion.
Claim 12
Dependent Claim
45 words
The circuit set forth in claim 9 wherein said first portion includes an integrator circuit receiving said input signals and said first processed signals being signals based upon integrating said input signals, and said quiescent signal state being a squelch state of said integrator circuit.
Claim 13
Dependent Claim
37 words
The circuit set forth in claim 9 wherein said second pOrtion includes a signal comparator receiving said first processed signals and said second reference means supplies said operational reference to said signal comparator for adjusting its operation.
Claim 14
Dependent Claim
31 words
The circuit set forth in claim 11 wherein said signal comparator compares said first processed signals with said operational reference and supplies an output signal indicating a greater or less comparison.
Claim 15
Dependent Claim
66 words
The circuit set forth in claim 12 wherein said input signals have a given periodicity; a clock in said first portion responsive to said input signal to supply a timing signal; said integrator circuit and said signal comparator responsive to said timing signal to time an input signal integration followed by a signal compare and integrator squelch; and said reference signals having a substantially constant amplitude.
Claim 16
Dependent Claim
109 words
The circuit set forth in claim 13 wherein said first portion has first and second ones of said integrator circuits, said timing signal having first and second halves in repetitive cycles; said integrator circuits respectively responsive to said first and second signal halves to alternately and successively integrate an input signal and squelch to said first reference signal such that said input signals are alternately and successively integrated on alternate ones of said integrator circuits; one of said integrator circuits supplying its first processed signal to said signal comparator; and additional output means responsive to said integrator circuits to supply an output signal during each said timing signal half.
Claim 17
Dependent Claim
100 words
The circuit set forth in claim 14 wherein each said integrator circuit includes: two signal integrating capacitors, each with an integrating end; a two-part squelch circuit, a first squelch circuit part having two transistor elements with emitter portions ohmically connected to said integrating ends, respectively, base portions commonly connected to said first reference means for receiving said first reference signal, a second squelch circuit part having two transistor elements with collector portions respectively ohmically connected to said integrating ends, and means in said squelch circuit responsive to said timing signal to switch said transistor elements between current conduction and nonconduction.
Claim 18
Dependent Claim
43 words
The circuit set forth in claim 14 further including in combination: first current sinks in each said integrator circuit; a second current sink in said second reference means; and said current sinks exhibiting substantially similar current amplitude variations with respect to environmental changes.
Claim 19
Dependent Claim
62 words
The circuit set forth in claim 9 further including in combination: a first current sink in said first portion and means in said first portion operative to utilize said first current sink for signal processing; a second current sink in said second reference means and operative in connection with establishing said operational reference; and said current sinks exhibiting similar current amplitude-to-temperature variations.
Claim 20
Dependent Claim
62 words
The circuit set forth in claim 17 wherein said first portion includes an integrator circuit, means connecting said first current sink to said integrator circuit in accordance with said input signal; and said second reference means transistor element having control and output portions, said control portion receiving said first reference signal and said second current sink being connected to said input portion.
Claim 21
Dependent Claim
80 words
A signal processing circuit having an integrator, the improvement including in combination: means establishing a squelch reference signal for said integrator; means to squelch said integrator to said squelch reference signal; and integrator output means having a threshold reference circuit receiving said squelch reference signal for establishing an output reference potential in said output means derived from said squelch reference signal and having a circuit portion responsive to saId integrator and said output threshold reference to supply an output signal.
Claim 22
Dependent Claim
80 words
A signal processing circuit having an integrator, the improvement including in combination: means establishing a squelch reference signal for said integrator; means to squelch said integrator to said squelch reference signal; and integrator output means having a threshold reference circuit receiving said squelch reference signal for establishing an output reference potential in said output means derived from said squelch reference signal and having a circuit portion responsive to saId integrator and said output threshold reference to supply an output signal.
Claim 23
Independent Claim
83 words
The method of processing a signal while employing signal integrating techniques, the improvement having the steps of: repetitively squelching an integrator circuit to a reference potential; intermediate said squelching, integrating an input signal in said integrator circuit by exchanging electrical current therewith at a given rate and in accordance with said input signal; deriving a threshold signal from said reference potential; and just prior to each squelch, sampling said integrator circuit integrated signal and comparing the integrated signal amplitude with said threshold signal.
Claim 24
Independent Claim
83 words
The method of processing a signal while employing signal integrating techniques, the improvement having the steps of: repetitively squelching an integrator circuit to a reference potential; intermediate said squelching, integrating an input signal in said integrator circuit by exchanging electrical current therewith at a given rate and in accordance with said input signal; deriving a threshold signal from said reference potential; and just prior to each squelch, sampling said integrator circuit integrated signal and comparing the integrated signal amplitude with said threshold signal.
Claim 25
Dependent Claim
54 words
The method set forth in claim 20 further including the steps of: establishing a current path and passing electrical current at a rate proportional to said given rate irrespective of temperature variations; and applying said reference potential to said current path and deriving said threshold signal from said reference potential via said current path.
Claim 26
Independent Claim
64 words
The method of squelching a two-capacitor integrator circuit; ohmically attaching matched transistor elements to said capacitors, respectively; and periodically applying a reference potential to said transistor elements while simultaneously connecting a current sink to both said capacitors for establishing identical constant current flows through both said transistor elements during a given squelch time for precisely establishing the same squelch potential on both said capacitors.
Claim 27
Independent Claim
64 words
The method of squelching a two-capacitor integrator circuit; ohmically attaching matched transistor elements to said capacitors, respectively; and periodically applying a reference potential to said transistor elements while simultaneously connecting a current sink to both said capacitors for establishing identical constant current flows through both said transistor elements during a given squelch time for precisely establishing the same squelch potential on both said capacitors.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-09-29 | 1979-03-31 | 1979-09-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-09-29 | 1983-03-31 | 1983-09-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-09-29 | 1987-03-31 | 1987-09-30 | $7700.00 | Window Closed / Lapsed |