Detection of digital data using integration techniques

Claim 2

A data detector, including in combination: means for receiving an amplitude-limited signal having first and second signal states; format means indicating that said signal represents data in a given format out of a plurality of possible formats; predetection processing and format selection means having a portion for each of said possible formats and responsive to said format means to activate a given portion to pass signals therethrough, said given portion supplying signals in an NRZ limited signal format corresponding to data represented in said given format; timing means responsive to said NRZ limited signal to generate a clock signal indicative of pairs of first and second successive sample times for said limited signal; first and second integration means each supplying an integrated signal, said first and second integration means being responsive to said clock signal respectively during said first and second sample times to integrate said limited signal, respectively, during said first and second sample times, each of said integration means being respectively nonresponsive to said limited signal at all other times; reference signal state recovery means in each said integration means for altering the integrated signal therein when the respective integration means are nonresponsive to said limited signal for altering each integratEd signal toward a reference signal value; separate means for combining said integrated signals from said first and second integration means and for combining said integrated signals from said third and fourth integrator means; and output means including post detection processing and format selection means having a portion for each of said possible formats and jointly responsive to said combined signals and to said format means for indicating data in accordance with the signal relationships therebetween and in accordance with said given format.

Claim 3

The subject matter of claim 1 wherein said clock signal has first and second signal states respectively indicating said first and second successive sample times; integrator clocking means electrically interposed between said timing means and each said integration means for selectively activating same in accordance with the signal states of said clock signal, a first integrator clocking means being responsive to said clock signal to actuate said first and third integration means to receive said limited signal and to respectively integrate said first and second signal states thereof and simultaneously actuating said second and fourth integration means to alter the integrated signals therein toward a reference state during substantially all of said first sample times; and said integrator clocking means being further responsive to said clocking signal being in said second signal state to cause said second and fourth integration means to be responsive to said limited signal and simultaneously causing said first and third integration means to alter the integrated signal toward a reference signal state during substantially all of said second sample time.

Claim 4

The subject matter set forth in claim 1 wherein said output means includes an amplitude voltage comparator responsive at predetermined times within said sample times to same combined signals for providing a binary output signal for indicating which of the two combined signals has the larger amplitude.

Claim 5

The subject matter set forth in claim 3 wherein said comparator means includes a bistable latch having first and second inputs for respectively switching the latch between first and second stable signal states; strobe means connected to said latch for selectively biasing said latch to an inactive circuit condition and further biasing said latch to an active circuit condition for a short period of time at the beginning of each of said sample times such that the combined signals bias the first and second inputs respectively for causing said latch to rapidly switch to one of said first or second signal stages during said short period.

Claim 6

Predetection integration for use with amplitude limited signals, a first-limited signal being supplied along a first line and a second limited signal being supplied along a second line; timing means responsive to one of said limited signals for generating a clocking signal having first and second signal states of respective durations substantially equal to predetermined durations of corresponding first and second signal states of said one limited signal; predetection processing means receiving said first and second limited signals for converting same to corresponding first and second intermediate data representing signals; control means operating said predetection processing means for varying the conversion and indicating format of said first and second limited signals such that said predetection processing means conversion varies in accordance with such indicated format; first integration means jointly responsive to said first intermediate signal being in a first signal state and to said clock signal being in a first signal state to integrate time duration of said intermediate signal being in said first signal state and being further responsive to said clock signal being in a second signal state to alter the integrated signal toward a reference state at a rate slightly greater than said rate of integration; second integration means jointly responsive to said first intermediate signal being in said first signal state and to said clock signal being in said second signal state to integrate the duration of said intermediate signal being in said first signal state and being further responsive to said clock signal being in said first signal state to alter the integrated signal toward a reference value at a rate slightly greater than the rate of integration; third integration means jointly responsive to said second intermediate signal being in a second signal state and to said clock signal being in said first signal state to integrate the duration of said second intermediate signal being in said second signal state and being further responsive to said clock signal being in said signal state to alter the integrated signal toward a reference state at a rate slightly greater than the rate of integration; fourth integration means jointly responsive to said second intermediate signal being in said second signal state and to said clock signal being in said second signal state to integrate the duration of said second intermediate signal being in said second signal state and being further responsive to said clock signal being in said first signal state to alter the integrated signal toward a reference state at a rate slightly greater than the rate of integration; signal combining means respectively combining the integrated signals from said first and second integration means for supplying a first combined signal indicating duration of the first signal state in said first intermediate signal and further combining integrated signals from said third and fourth integration means for supplying a second combined signal indicating the duration of said second intermediate signal being in said second signal state; and post detection processing means responsive to said control means for altering said combined signals indicating data in accordance with said format wherein at least one of said conversions includes supplying said signals without altering the timing thereof.

Claim 7

Predetection integration for use with amplitude limited signals, a first-limited signal being supplied along a first line and a second limited signal being supplied along a second line; timing means responsive to one of said limited signals for generating a clocking signal having first and second signal states of respective durations substantially equal to predetermined durations of corresponding first and second signal states of said one limited signal; predetection processing means receiving said first and second limited signals for converting same to corresponding first and second intermediate data representing signals; control means operating said predetection processing means for varying the conversion and indicating format of said first and second limited signals such that said predetection processing means conversion varies in accordance with such indicated format; first integration means jointly responsive to said first intermediate signal being in a first signal state and to said clock signal being in a first signal state to integrate time duration of said intermediate signal being in said first signal state and being further responsive to said clock signal being in a second signal state to alter the integrated signal toward a reference state at a rate slightly greater than said rate of integration; second integration means jointly responsive to said first intermediate signal being in said first signal state and to said clock signal being in said second signal state to integrate the duration of said intermediate signal being in said first signal state and being further responsive to said clock signal being in said first signal state to alter the integrated signal toward a reference value at a rate slightly greater than the rate of integration; third integration means jointly responsive to said second intermediate signal being in a second signal state and to said clock signal being in said first signal state to integrate the duration of said second intermediate signal being in said second signal state and being further responsive to said clock signal being in said signal state to alter the integrated signal toward a reference state at a rate slightly greater than the rate of integration; fourth integration means jointly responsive to said second intermediate signal being in said second signal state and to said clock signal being in said second signal state to integrate the duration of said second intermediate signal being in said second signal state and being further responsive to said clock signal being in said first signal state to alter the integrated signal toward a reference state at a rate slightly greater than the rate of integration; signal combining means respectively combining the integrated signals from said first and second integration means for supplying a first combined signal indicating duration of the first signal state in said first intermediate signal and further combining integrated signals from said third and fourth integration means for supplying a second combined signal indicating the duration of said second intermediate signal being in said second signal state; and post detection processing means responsive to said control means for altering said combined signals indicating data in accordance with said format wherein at least one of said conversions includes supplying said signals without altering the timing thereof.

Claim 8

The subject matter set forth in claim 5 wherein said post detection processing circuit comprises: a binary latch having zero and one signal indicating output signal states, a set input receiving said first combined signal, and a reset input receiving said second combined signal; first, second, third, and fourth AND circuit means, each supplying output signal, said first and second AND circuit means receiving said one output signal state of said binary trigger, said third and fourth AND circuit means receiving the zero output of said binary trigger, said second and third AND circuit means respectively receiving said first combined signal, said first and fourth AND circuit means receiving said second combined signal; means combining the output signals of said second and fourth AND circuit means to supply a first data indicating signal and means combining the output signals of said first and third AND circuit means to supply a second data indicating signal; said control means selectively actuating said binary latch to said reset state; and said predetection processing circuits including phase demodulating means and responsive to said control circuit means to phase demodulate said first and second limited data signals whenever said control circuit is holding said binary trigger to said reset state.

Claim 11

The method of claim 7 wherein said input digital signal may have more than one state change in each time period, the improved method further including the steps for generating said NRZ signal for a second one of said formats of: generating a reference digital signal having predetermined cyclic signal-state changes related to said input digital signal-state changes; logically combining said input and reference digital signals to produce a third digital NRZ signal having fewer state changes per time period than said input digital signal; then integrating said third digital signal in place of integrating said input digital signal; and supplying said integrated signal as an output signal without said selective alteration.

Claim 12

A digital signal detector including in combination: data signal receiving means including format control means selectively altering received signals to generate intermediate first and second digital signal-representing data signals; first and second integrators, each integrator having + and -integration circuits, said integrations respectively receiving said first and second digital signals; clock means supplying digital clock signals to said integration circuits for alternately activating said integration circuits to integrate said digital signals to integrated signals; means receiving said integrated signals and combining same in a predetermined manner and responsive to one of said clock signals to supply output signals indicative of the signal relationships of said intermediate digital signals as represented by said integrated signals; and data output means including data representing altering means selectively altering said integrated signals to represent data in accordance with said format control means and said data signal receiving means.

Claim 13

A digital signal detector including in combination: data signal receiving means including format control means selectively altering received signals to generate intermediate first and second digital signal-representing data signals; first and second integrators, each integrator having + and -integration circuits, said integrations respectively receiving said first and second digital signals; clock means supplying digital clock signals to said integration circuits for alternately activating said integration circuits to integrate said digital signals to integrated signals; means receiving said integrated signals and combining same in a predetermined manner and responsive to one of said clock signals to supply output signals indicative of the signal relationships of said intermediate digital signals as represented by said integrated signals; and data output means including data representing altering means selectively altering said integrated signals to represent data in accordance with said format control means and said data signal receiving means.

Claim 14

The detector set forth in claim 9 wherein said receiving means includes two differential comparison circuits, two summing means for each said comparison circuits, and each said summing means combining two of said integrated signals and supplying such combined signals to the respective differential comparison circuit, said combining means activating both said differential comparison circuits to supply an output signal each time said clock signals change signal states; one of said comparison circuits supplying a data indicating signal as its output signal; and data processing means receiving said data indicating signal for processing same and responsive to said output signal from another of said comparison circuits to selectively alter said processing in accordance therewith.

Claim 15

Synchronous demodulation employing integration, including the following steps in combination: supplying a timing signal; supplying data signals to be synchronously demodulated with respect to said timing signals; combining said timing signal and said data signals to generate plural distinct signal amplitudes including integrating said data signals with respect to said timing signals; in timed relation to said timing signal, combining said plural distinct signal amplitudes into two output signals timed by said timing signal, one output signal representing said data signal in a synchronous demodulaTed relation to said timing signals and another output signal indicating an error status of said data signal; and combining said two output signals in a predetermined manner to supply a correct output data signal.

Claim 16

Synchronous demodulation employing integration, including the following steps in combination: supplying a timing signal; supplying data signals to be synchronously demodulated with respect to said timing signals; combining said timing signal and said data signals to generate plural distinct signal amplitudes including integrating said data signals with respect to said timing signals; in timed relation to said timing signal, combining said plural distinct signal amplitudes into two output signals timed by said timing signal, one output signal representing said data signal in a synchronous demodulaTed relation to said timing signals and another output signal indicating an error status of said data signal; and combining said two output signals in a predetermined manner to supply a correct output data signal.

Claim 17

An electrical signal processing circuit, including in combination: means for differentially receiving a signal to be processed; means for selectively altering said differentially received signal to supply an intermediate differential signal; a differentially operating timing circuit for defining successive time periods of signal processing; first and second differentially connected switches each with first and second differential inputs and outputs differentially receiving said signal to be processed, and said switches being alternately actuated in said successive time periods between electrical current conductive and nonconductive states by said timing circuit and further responsive to said intermediate signal to alter one of said states; integration signal storage means extending between said outputs of said differentially connected switches, respectively; means for detecting electrical signals in said storage means in timed relation to said time periods; and means operatively associated with said selective altering means to selectively convert said detected electrical signals to a different data-indicating state.

Claim 18

An electrical signal processing circuit, including in combination: means for differentially receiving a signal to be processed; means for selectively altering said differentially received signal to supply an intermediate differential signal; a differentially operating timing circuit for defining successive time periods of signal processing; first and second differentially connected switches each with first and second differential inputs and outputs differentially receiving said signal to be processed, and said switches being alternately actuated in said successive time periods between electrical current conductive and nonconductive states by said timing circuit and further responsive to said intermediate signal to alter one of said states; integration signal storage means extending between said outputs of said differentially connected switches, respectively; means for detecting electrical signals in said storage means in timed relation to said time periods; and means operatively associated with said selective altering means to selectively convert said detected electrical signals to a different data-indicating state.

Claim 19

A signal processing system for processing digital information-bearing signals of different character, means for reading recorded digital signals from a record media, the improved system including in combination: first means indicating the character of said digital signals read from said record media; second means responsive to said indication to convert said read digital signals to NRZ or NRZI intermediate signals, some of said intermediate signals being NRZ and others NRZI; an NRZ data detector receiving said intermediate signals to supply detected NRZ 1 and 0 signals independent of said NRZ and NRZI types; and third means receiving said detected NRZ 1 and 0 signals and responsive to said indication to convert said NRZ 1''s and 0''s to NRZI 1''s and 0''s when said intermediate signals are NRZI type.

Claim 20

A signal processing system for processing digital information-bearing signals of different character, means for reading recorded digital signals from a record media, the improved system including in combination: first means indicating the character of said digital signals read from said record media; second means responsive to said indication to convert said read digital signals to NRZ or NRZI intermediate signals, some of said intermediate signals being NRZ and others NRZI; an NRZ data detector receiving said intermediate signals to supply detected NRZ 1 and 0 signals independent of said NRZ and NRZI types; and third means receiving said detected NRZ 1 and 0 signals and responsive to said indication to convert said NRZ 1''s and 0''s to NRZI 1''s and 0''s when said intermediate signals are NRZI type.

Claim 21

A readback system for a digital data recorder receiving signals from a record media which can represent digital information in one of a plurality of signal formats, amplitude-limiting means transferring said digital data signals as amplitude-limited signals to thereby represent information as a succession of signal-state changes; the improvement including the combination: control means indicating one of said plurality of signal formats; predetection processor including logic circuits responsive to said indication to selectively convert said signals from said one format to an intermediate signal format representing information as a succession of signal-state changes different from said one signal format and to pass other signals from other formats without conversion; a data detector responsive to said intermediate signals to supply detected intermediate 1 and 0 signals which may or may not represent information as recorded; and a post detection processor receiving said detected intermediate 1 and 0 signals and responsive to said indication to selectively further convert said detected intermediate 1 and 0 signals to signals having another succession of signal-state changes to truly represent recorded information while responsive to at least one of said indications not to further convert said detected intermediate 1 and 0 signals.

Claim 22

A readback system for a digital data recorder receiving signals from a record media which can represent digital information in one of a plurality of signal formats, amplitude-limiting means transferring said digital data signals as amplitude-limited signals to thereby represent information as a succession of signal-state changes; the improvement including the combination: control means indicating one of said plurality of signal formats; predetection processor including logic circuits responsive to said indication to selectively convert said signals from said one format to an intermediate signal format representing information as a succession of signal-state changes different from said one signal format and to pass other signals from other formats without conversion; a data detector responsive to said intermediate signals to supply detected intermediate 1 and 0 signals which may or may not represent information as recorded; and a post detection processor receiving said detected intermediate 1 and 0 signals and responsive to said indication to selectively further convert said detected intermediate 1 and 0 signals to signals having another succession of signal-state changes to truly represent recorded information while responsive to at least one of said indications not to further convert said detected intermediate 1 and 0 signals.

Claim 23

The readback system set forth in claim 14 wherein the record media includes format indicating signals, means for detecting said format indicating signals to actuate said control means; timing means for timing said processors and said data detector; the improvement further including in combination: said timing means supplying a plurality of timing signals all of diFferent frequencies; means in said control means electrically interposed between said timing means and said data detector to select one of a plurality of timing signals and supplying said selected timing signal to said data detector in accordance with said indication.

Claim 24

The readback system set forth in claim 15 further including in combination: phase error detecting means responsive to said amplitude-limited signals and to a given one of said timing means timing signals to indicate a phase error upon occurrence of predetermined timing relationships between said given one timing signal to signal a phase error; means in said control means responsive to a given one of said indications to pass said signaled phase error; and means responsive to said signaled phase error and said further converted signals to supply output data signals.

Claim 25

The readback system set forth in claim 14 further including in combination: timing means supplying first and second timing signals respectively indicating alternate successive periods to said data detector for timing same to supply plural detection signals in successive first and second alternate ones of said periods and supplying a sampling pulse at the end of each said periods, a succession of said detection signals indicating detected intermediate signals; a first comparator portion in said data detector receiving said detection signals, comprising two differentially connected comparator transistor element circuits having an output and responsive to said first and second timing signals, respectively, to select said detection signals, a comparator latch circuit including cross-coupled transistor elements having a common emitter connection and having a given latch input, said comparator circuit outputs connected to said given latch input, a transistor element circuit connected to said common emitter connection and responsive to each said sample pulse to activate said comparator latch for supplying said detected intermediate 1 and 0 signals in response to predetermined amplitudes of said detection signals; a second comparator portion in said data detector receiving said detection signals, comprising two second differentially connected comparator transistor element pair circuits having an output and responsive to said first and second timing signals, respectively, to select said detection signals, a second comparator latch circuit including second cross-coupled transistor elements having a common emitter connection and having first and second latch inputs, said second comparator circuit outputs connected to said first latch input; a reference source connected to said second latch input for indicating an error threshold, means in said comparator latch responsive to said relative amplitudes at said inputs to supply an activating signal for triggering said comparator latch to an error-indicating state; and a second transistor element circuit connected to said common emitter connection and responsive to each said sample pulses to activate said second comparator latch for supplying either an error or error-free indicating signal for simultaneously supplied detected intermediate 1 and 0 signals.

Claim 26

A signal processing circuit for processing digital data signals of diverse types, each type representing data by different sequences of signal-state changes for representing the same data, the improvement including in combination: means indicating which type of digital data signal is to be received; predetection processing means responsive to said indication to selectively alter said sequences of signal-state changes to an intermediate sequence of signal-state changes; a detector for detecting said intermediate signal-state changes to supply timed output signals indicating said intermediate signal-state changes; and post detection processing means responsive to said indication to selectively alter said timed output signals to supply output signals indicating said data.

Claim 27

A signal processing circuit for processing digital data signals of diverse types, each type representing data by different sequences of signal-state changes for representing the same data, the improvement including in combination: means indicating which type of digital data signal is to be received; predetection processing means responsive to said indication to selectively alter said sequences of signal-state changes to an intermediate sequence of signal-state changes; a detector for detecting said intermediate signal-state changes to supply timed output signals indicating said intermediate signal-state changes; and post detection processing means responsive to said indication to selectively alter said timed output signals to supply output signals indicating said data.

Claim 28

A digital signal processing circuit, including in combination: an alternate cycle integrator apparatus for receiving and detecting NRZ type digital signals and supplying output digital signals; detection processing means connected to said apparatus for selectively exchanging signals therewith and selectively altering digital signals between NRZ type and another type; a first phase error circuit receiving said output digital signal from said apparatus to indicate phase errors in said NRZ type signals; a second phase error circuit responsive to said another type digital signals to detect and indicate phase errors in such another type digital signals; and timing signal generator means responsive to one of said digital signals to supply timing digital signals to said apparatus for enabling alternate cycle operation, said processing means and said phase error circuits to coordinate operation thereof with said one digital signal.

Claim 29

A digital signal processing circuit, including in combination: an alternate cycle integrator apparatus for receiving and detecting NRZ type digital signals and supplying output digital signals; detection processing means connected to said apparatus for selectively exchanging signals therewith and selectively altering digital signals between NRZ type and another type; a first phase error circuit receiving said output digital signal from said apparatus to indicate phase errors in said NRZ type signals; a second phase error circuit responsive to said another type digital signals to detect and indicate phase errors in such another type digital signals; and timing signal generator means responsive to one of said digital signals to supply timing digital signals to said apparatus for enabling alternate cycle operation, said processing means and said phase error circuits to coordinate operation thereof with said one digital signal.