Patent US3909119A successfully refreshed from Google Patents.
US3909119A
Expired / Lapsed
US
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Guarded planar PN junction semiconductor device
Assignee: Westinghouse Electric Corp
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Filing: 1974-02-06
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Granted: 1975-09-30
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Expires: 1994-02-06
Abstract
Abstract A semiconductor device with at least one planar PN junction is provided in a semiconductor body having at least one major surface. The body has first and second impurity regions of opposite conductivity type forming a first PN junction therebetween. The first impurity region is positioned adjoining the major surface, and the second impurity region is positioned in interior portions of the body adjoining the first impurity region. The second impurity region has an impurity concentration profile and thickness to support a space-charge region on application of a given reverse bias voltage across the PN junction. A third impurity region is positioned in the semiconductor body adjoining the major surface around the first impurity region, and at least laterally encompassing the first and second impurity regions to form a second PN junction with the first impurity region, said second PN junction extending contiguously around the first PN junction and adjoining the major surface around and spaced from the second impurity region. The third impurity region has an impurity concentration profile and thickness to more than support the space-charge region formed at the second PN junction on application of said reverse bias voltage across the PN junction so that the blocking voltage of the device can be controlled by the avalanche breakdown and punch-through voltage at the second impurity region. For high voltage applications, field limiting rings can be positioned in the semiconductor body adjoining the major surface around and spaced from the second PN junction to form additional PN junctions with the third impurity region and to divide the electric field on application of a given applied voltage.
Inventors
- 👤 Elden D Wolley
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 14:41
CPC Classifications
H; H10; H10D; H10D8/00; H10D10/00; H10D10/40; H10D10/421; H10D62/00; H10D62/10; H10D62/102; H10D62/103; H10D62/105; H10D62/108; H10D62/124; H10D62/125; H10D99/00; Y; Y10; Y10S; Y10S148/00; Y10S148/035; Y10S148/049; Y10S148/05; Y10S148/085; Y10S148/145; Y10S257/00; Y10S257/913
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
251 words
A semiconductor device with at least one planar PN junction comprising: A. a semiconductor body having at least one major surface; B. a first impurity region of a given conductivity type positioned in the body adjoining selected portions of the major surface; C. a second impurity region of opposite conductivity type from the first impurity region positioned in interior portions of the body adjoining the first impurity region to form a first PN junction therewith, said second impurity region having a lower impurity concentration than said first impurity region and a thickness to support a space-charge region on application of a given reverse bias voltage across said first PN junction; D. a third impurity region of opposite conductivity type from the first impurity region positioned in the body adjoining the major surface around and adjoining the first impurity region and at least laterally contiguously around the first and second impurity region to form a second PN junction with the first impurity region, said second PN junction extending contiguously from said first PN junction to adjoin the major surface around and axially spaced from the second impurity region; E. said third impurity region having an impurity concentration profile and thickness to more than support the space-charge region formed at the second PN junction on application of said given reverse bias voltage across said second PN junction; and F. an electrode layer of electrically conductive material disposed on the major surface of the body and making ohmic contact with the first impurity region.
Claim 2
Dependent Claim
251 words
A semiconductor device with at least one planar PN junction comprising: A. a semiconductor body having at least one major surface; B. a first impurity region of a given conductivity type positioned in the body adjoining selected portions of the major surface; C. a second impurity region of opposite conductivity type from the first impurity region positioned in interior portions of the body adjoining the first impurity region to form a first PN junction therewith, said second impurity region having a lower impurity concentration than said first impurity region and a thickness to support a space-charge region on application of a given reverse bias voltage across said first PN junction; D. a third impurity region of opposite conductivity type from the first impurity region positioned in the body adjoining the major surface around and adjoining the first impurity region and at least laterally contiguously around the first and second impurity region to form a second PN junction with the first impurity region, said second PN junction extending contiguously from said first PN junction to adjoin the major surface around and axially spaced from the second impurity region; E. said third impurity region having an impurity concentration profile and thickness to more than support the space-charge region formed at the second PN junction on application of said given reverse bias voltage across said second PN junction; and F. an electrode layer of electrically conductive material disposed on the major surface of the body and making ohmic contact with the first impurity region.
Claim 3
Dependent Claim
52 words
A semiconductor device with at least one planar PN junction as set forth in claim 1 wherein: the impurity concentration profile of the third impurity region is substantially uniform, and the resistivity of the third impurity region is at least two times greater than the average resistivity of the second impurity region.
Claim 4
Dependent Claim
66 words
A semiconductor device with at least one planar PN junction as set forth in claim 1 comprising in addition: G. a fourth impurity region positioned in the semiconductor body adjoining the major surface around and spaced from the second PN junction, said fourth impurity region being of opposite conductivity type from the third impurity region and forming a third PN junction with the third impurity region.
Claim 5
Dependent Claim
84 words
A semiconductor device with at least one planar PN junction as set forth in claim 1 comprising in addition: G. an insulator layer of an electrically insulating material positioned on the major surface of the semiconductor body around said electrode layer; and H. an extension portion of said electrode layer extending from said electrode layer over the insulator layer and the second PN junction to axially extend a space charge region of the second PN junction at the major surface of the semiconductor body.
Claim 6
Dependent Claim
52 words
A semiconductor device with at least one planar PN junction as set forth in claim 1 wherein: the impurity concentration profile of the third impurity region is substantially uniform, and the resistivity of the third impurity region is at least two times greater than the average resistivity of the second impurity region.
Claim 7
Dependent Claim
280 words
A semiconductor device with at least one planar PN junction comprising: A. a degenerate semiconductor substrate capable of electrically conducting; B. an epitaxial semiconductor layer formed on said major surface of the semiconductor substrate to form a semiconductor body having a major surface; C. a first impurity region of a given conductivity type positioned in the epitaxial layer adjoining selected portions of said maJor surface. D. a second impurity region of opposite conductivity type from the first impurity region positioned in interior portions of the epitaxial layer adjoining the first impurity region to form a first PN junction therewith, said second impurity region having a lower impurity concentration than said first impurity region and a thickness to support a space-charge region on application of a given reverse bias voltage across said first PN junction; E. a third impurity region of opposite conductivity type from the first impurity region positioned in the epitaxial layer adjoining said major surface around and adjoining the first impurity region and at least laterally contiguously around the first and second impurity region through the epitaxial layer to form a second PN junction with the first impurity region, said second PN junction extending contiguously from said first PN junction to adjoin said major surface around and axially spaced from the second impurity region; F. said third impurity region having an impurity concentration profile and thickness to more than support the space-charge region formed at the second PN junction on application of said given reverse bias voltage across said second PN junction; and G. an electrode layer of electrically conductive material disposed on said major surface of the epitaxial layer making ohmic contact with the first impurity region.
Claim 8
Dependent Claim
280 words
A semiconductor device with at least one planar PN junction comprising: A. a degenerate semiconductor substrate capable of electrically conducting; B. an epitaxial semiconductor layer formed on said major surface of the semiconductor substrate to form a semiconductor body having a major surface; C. a first impurity region of a given conductivity type positioned in the epitaxial layer adjoining selected portions of said maJor surface. D. a second impurity region of opposite conductivity type from the first impurity region positioned in interior portions of the epitaxial layer adjoining the first impurity region to form a first PN junction therewith, said second impurity region having a lower impurity concentration than said first impurity region and a thickness to support a space-charge region on application of a given reverse bias voltage across said first PN junction; E. a third impurity region of opposite conductivity type from the first impurity region positioned in the epitaxial layer adjoining said major surface around and adjoining the first impurity region and at least laterally contiguously around the first and second impurity region through the epitaxial layer to form a second PN junction with the first impurity region, said second PN junction extending contiguously from said first PN junction to adjoin said major surface around and axially spaced from the second impurity region; F. said third impurity region having an impurity concentration profile and thickness to more than support the space-charge region formed at the second PN junction on application of said given reverse bias voltage across said second PN junction; and G. an electrode layer of electrically conductive material disposed on said major surface of the epitaxial layer making ohmic contact with the first impurity region.
Claim 9
Dependent Claim
52 words
A semiconductor device with at least one planar PN junction as set forth in claim 6 wherein: the impurity concentration profile of the third impurity region is substantially uniform, and the resistivity of the third impurity region is at least two times greater than the average resistivity of the second impurity region.
Claim 10
Dependent Claim
39 words
A semiconductor device with at least one planar PN junction as set forth in claim 6 wherein: said second impurity region extends through the epitaxial layer from said first PN junction to the major surface of the semiconductor substrate.
Claim 11
Dependent Claim
59 words
A semiconductor device with at least one planar PN junction as set forth in claim 6 comprising in addition: H. a further highly conductive impurity region of the same conductivity as the second impurity region in the interior portions of the epitaxial layer extending between and adjoining the second impurity region and the major surface of the semiconductor substrate.
References Cited (Backward Citations)
US3663874A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-09-29 | 1979-03-31 | 1979-09-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-09-29 | 1983-03-31 | 1983-09-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-09-29 | 1987-03-31 | 1987-09-30 | $7700.00 | Window Closed / Lapsed |