Digital resolver filter and receiver using same

Claim 2

A digital filter of the purely recursive type, comprising a recursive loop including: at least one adder stage and a delay means the output of which is fed back to the input of said adder stage for extracting from the input signal a sine wave component, said recursive loop further including a means for shifting the phase of said sine wave component by a predetermined increment value, said means for shifting the phase of said sine component including means for extracting from said delay line signal samples of the signal which are out of phase relatively to the sample coming out of said line, by 1/4 and 3/4 of a period, respectively; means for subtracting said samples from each other; weighting means and means for applying to the result of said subtracting operation a weighting coefficient proportional to the desired phase shifting increment before applying the new sample thus determined to the input of said adder together with the sample coming out of said shift reGister; and means for repeating this operation until the first sample processed appears in the last stage of said shift register.

Claim 3

A digital resolver and filter comprising: a purely recursive digital filter including at least a first adder, to one of the inputs of which are fed samples of the signal to be filtered; a multi-stage shift register, to the input of which are fed samples of the filtered signal from the output of said first adder, and the output of which is fed back to one of the inputs of said first adder; and, weighting means at the outputs of the stages of said shift register for weighting the magnitude of said samples of said filtered signals; and a resolver circuit means connected to the weighted signal outputs of said shift register and to a phase reference signal for determining the phase difference between said filtered signal and said given local reference signal, and for shifting the phase of said filtered signal still stored in said shift register so as to eliminate said phase difference.

Claim 4

A digital resolver and filter comprising: a purely recursive digital filter including at least a first adder, to one of the inputs of which are fed samples of the signal to be filtered; a multi-stage shift register, to the input of which are fed samples of the filtered signal from the output of said first adder, and the output of which is fed back to one of the inputs of said first adder; and, weighting means at the outputs of the stages of said shift register for weighting the magnitude of said samples of said filtered signals; and a resolver circuit means connected to the weighted signal outputs of said shift register and to a phase reference signal for determining the phase difference between said filtered signal and said given local reference signal, and for shifting the phase of said filtered signal still stored in said shift register so as to eliminate said phase difference.

Claim 5

A device as described in claim 1, wherein: said means for determining said phase difference includes another adder to at least two inputs of which are fed signals taken at the taps located between the stages of said shift register, said signals being weighted in such a way as to obtain an expression of the cosine of said phase difference at the output of said another adder.

Claim 6

A recursive digital filtering and phase shifting device as described in claim 3, further including: means for switching from the filtering function to the phase shifting function and vice versa.

Claim 7

Apparatus as described in claim 3, wherein: said means for eliminating said phase differential includes means for recirculating through said first adder samples of the filtered signal stored in said shift register, both directly and after they have passed through said another adder and have been weighted by a coefficient proportional to said phase difference.

Claim 8

A recursive digital filtering and phase shifting device as described in claim 5, further including: means for switching from the filtering function to the phase shifting function and vice versa.

Claim 9

A recursive digital filtering and phase shifting device as described in claim 1, further including: means for switching from the filtering function to the phase shifting function and vice versa.

Claim 10

A device as described in claim 1, wherein: said means for determining said phase difference includes a second adder to at least two inputs of which are fed signals taken at the taps located between the stages of said shift register, said signals being weighted by said weighting means in such a way as to obtain an expresssion of the sine of said phase difference at the output of said second adder.

Claim 11

Apparatus as described in claim 8, wherein: said means for eliminating said phase differential includes means for recirculating through said first adder samples of the filtered signal stored in said shift register, both directly and after they have passed through said second adder and have been weighted by a coefficient proportional to said phase difference.

Claim 12

A recursive digital filtering and phase shifting device as described in claim 9, further including: means for switching from the filtering function to the phase shifting function and vice versa.

Claim 13

A recursive digital filtering and phase shifting device as described in claim 8, further including: means for switching from the filtering function to the phase shifting function and vice versa.

Claim 14

Apparatus for recovering the information associated with the synchronization of the clock of a receiver operating in the amplitude and/or phase modulation mode, comprising: a resolver filter for extracting the clock information contained in the received signal envelope and for determining its phase relative to a given reference and for correcting the phase of said clock informatioN by recirculating the data within said resolver filter while simultaneously correcting said reference; said resolver filter comprising: a purely recursive digital filter including at least a first adder, to one of the inputs of which are fed samples of the signal to be filtered; a multi-stage shift register, to the input of which are fed samples of the filtered signal from the output of said first adder, and the output of which is fed back to one of the inputs of said first adder; and weighting means at the outputs of the stages of said shift register for weighting the magnitude of said samples of said filtered signals; and a resolver circuit means connected to the weighted signal outputs of said shift register and to a phase reference signal for determining the phase difference between said filtered signal and said given local refrence signal, and for shifting the phase of said filtered signal still stored in said shift register so as to eliminate said phase difference.

Claim 15

Apparatus for recovering the information associated with the synchronization of the clock of a receiver operating in the amplitude and/or phase modulation mode, comprising: a resolver filter for extracting the clock information contained in the received signal envelope and for determining its phase relative to a given reference and for correcting the phase of said clock informatioN by recirculating the data within said resolver filter while simultaneously correcting said reference; said resolver filter comprising: a purely recursive digital filter including at least a first adder, to one of the inputs of which are fed samples of the signal to be filtered; a multi-stage shift register, to the input of which are fed samples of the filtered signal from the output of said first adder, and the output of which is fed back to one of the inputs of said first adder; and weighting means at the outputs of the stages of said shift register for weighting the magnitude of said samples of said filtered signals; and a resolver circuit means connected to the weighted signal outputs of said shift register and to a phase reference signal for determining the phase difference between said filtered signal and said given local refrence signal, and for shifting the phase of said filtered signal still stored in said shift register so as to eliminate said phase difference.

Claim 16

Apparatus as described in claim 12, wherein: said means for determining said phase difference includes a second adder to at least two inputs of which are fed signals taken at the taps located between the stages of said shift register, said signals being weighted by said weighting means in such a way as to obtain an expression of the sine of said phase difference at the output of said second adder.

Claim 17

Apparatus as described in claim 13, further including: means for switching from the filtering function to the phase shifting function and vice versa.

Claim 18

Apparatus as described in claim 13, wherein: said means for eliminating said phase differential includes means for recirculating through said first adder samples of the filtered signal stored in said shift register, both directly and after they have passed through said second adder and have been weighted by a coefficient proportional to said phase difference.

Claim 19

Apparatus as described in claim 15, further including: means for switching from the filtering function to the phase shifting function and vice versa.

Claim 20

Apparatus as described in claim 12, wherein: said means for determining said phase difference includes another adder to at least two inputs of which are fed signals taken at the taps located between the stages of said shift register, said signals being weighted in such a way as to obtain an expression of the cosine of said phase difference at the output of said another adder.

Claim 21

Apparatus as described in claim 17, wherein: said means for eliminating said phase, differential includes means for recirculating through said first adder samples of the filtered signal stored in said shift register, both directly and after they have passed through said another adder and have been weighted by a coefficient proportional to said phase difference.

Claim 22

Apparatus as described in claim 17, further including: means for switching from the filtering function to the phase shifting function and vice versa.

Claim 23

Apparatus as described in claim 12, wherein said means for eliminating said phase differential includes: at least one adder stage and a delay means, the output of which is fed back to the input of said adder stage for extracting from the input signal a sine wave component, said recursive loop further including a means for shifting the phase of said sine wave component by a predetermined increment value, said means for shifting the phase of said sine component including means for extracting from said delay line signal samples of the signal which are out of phase relatively to the sample coming out of said line, by 1/4 and 3/4 of a period, respectively; means for subtracting said samples from each other; weighting means and means for applying to the result of said subtracting operation a weighting coefficient proportional to the desired phase shifting increment before applying the new sample thus determined to the input of said adder together witH the sample coming out of said shift register; and means for repeating this operation until the first sample processed appears in the last stage of said shift register.

Claim 24

Apparatus as described in claim 12, further including: means for switching from the filtered function to the phase shifting function and vice versa.

Claim 25

Apparatus for recovering the clock information contained in received analog signals and for synchronizing the local clock of a data receiver operating in the amplitude and/or phase modulation mode, comprising: conversion means under the control of said local clock for converting the analog signals applied to said receiver into digital signal samples; digital means for determining the envelope of said samples; means for applying said envelope to a digital resolver and filter while said resolver and filter is operating as a filter, said digital resolver and filter comprising: a purely recursive digital filter including at least a first adder, to one of the inputs of which are fed samples of the signal to be filtered; a multi-stage shift register, to the input of which are fed samples of the filtered signal from the output of said first adder, and the output of which is fed back to one of the inputs of said first adder; and, weighting means at the outputs of the stages of said shift register for weighting the magnitude of said samples of said filtered signals; and a resolver circuit means connected to the weighted signal outputs of said shift register and to a phase reference signal for determining the phase difference between said filtered signal and said given local reference signal, and for shifting the phase of said filtered signal still stored in said shift register so as to eliminate said phase difference; means for determining the phase of said filtered signals relative to given characteristic instants of said clock information contained in said received signals; means for recirculating said samples in said shift register of said digital resolver and filter while it is operating as a resolver circuit, thereby to shift the phase of said signal sampled by a given incremental value; and means for adjusting the local clock of said receiver simultaneously with said shifting operation of the phase of said samples so as to compensate for the phase error detected by said resolver circuit.

Claim 26

Apparatus for recovering the clock information contained in received analog signals and for synchronizing the local clock of a data receiver operating in the amplitude and/or phase modulation mode, comprising: conversion means under the control of said local clock for converting the analog signals applied to said receiver into digital signal samples; digital means for determining the envelope of said samples; means for applying said envelope to a digital resolver and filter while said resolver and filter is operating as a filter, said digital resolver and filter comprising: a purely recursive digital filter including at least a first adder, to one of the inputs of which are fed samples of the signal to be filtered; a multi-stage shift register, to the input of which are fed samples of the filtered signal from the output of said first adder, and the output of which is fed back to one of the inputs of said first adder; and, weighting means at the outputs of the stages of said shift register for weighting the magnitude of said samples of said filtered signals; and a resolver circuit means connected to the weighted signal outputs of said shift register and to a phase reference signal for determining the phase difference between said filtered signal and said given local reference signal, and for shifting the phase of said filtered signal still stored in said shift register so as to eliminate said phase difference; means for determining the phase of said filtered signals relative to given characteristic instants of said clock information contained in said received signals; means for recirculating said samples in said shift register of said digital resolver and filter while it is operating as a resolver circuit, thereby to shift the phase of said signal sampled by a given incremental value; and means for adjusting the local clock of said receiver simultaneously with said shifting operation of the phase of said samples so as to compensate for the phase error detected by said resolver circuit.

Claim 27

Apparatus as described in claim 22, wherein: said means for determining said phase difference includes a second adder to at least two inputs of which are fed signals taken at the taps located between the stages of said shift register, said signals being weighted by said weighting means in such a way as to obtain an expression of the sine of said phase difference at the output of said second adder.

Claim 28

Apparatus as described in claim 23, wherein: said means for eliminating said phase differential includes means for recirculating through said first adder samples of the filtered signals stored in said shift register, both directly and after they have passed through said second adder and have been weighted by a coefficient proportional to said phase difference.

Claim 29

Apparatus as described in claim 22, wherein: said means for determining said phase difference includes another adder to at least two inputs of which are fed signals taken at the taps located between the stages of said shift register, said signals being weighted in such a way as to obtain an expression of the cosine of said phase difference at the output of said third adder.

Claim 30

Apparatus as described in claim 25, wherein: said means for eliminating said phase differential includes means for recirculating through said first adder samples of the filtered signal stored in said shift register, both directly and after they have passed through said another adder and have been weighted by a coefficient proportional to said phase difference.

Claim 31

Apparatus as described in claim 22, further including: at least one adder stage and a delay means the output of which is fed back to the input of said adder stage for extracting from the input signal a sine wave component, said recursive loop further including a means for shifting the phase of said sine wave component by a predetermined increment value, said means for shifting the phase of said sine component including means for extracting from said delay line signal samples of the signal which are out of phase relatively to the sample coming out of said line, by 1/4 and 3/4 of a period, respectively; means for subtracting said samples from each other; weighting means and means for applying to the result of said subtracting operation a weighting coefficient proportional to the desired phase shifting increment before applying the new sample thus determined to the input of said adder together with the sample coming out of said shift register; and means for repeating this operation until the first sample processed appears in the last stage of said shift register.