Predictive conversion between self-correlated analog signal and corresponding digital signal according to digital companded delta modulation

Claim 2

A converter for carrying out conversion between a digital signal of a certain type and a predicted analog signal, said digital signal consisting of a sequence of one-bit pulses each having a value dependent upon a comparison at a sample period of a self-correlated analog signal and said predicted analog signal, said converter comprising, a. digital step size generator means responsive to each said one bit pulse and a number of immediately preceding one bit pulses for generating a digital step size signal representing one of at least three predetermined step sizes, the particular digital step size signal generated being dependent upon the pattern of said one bit pulses, b. a delay circuit for delaying said digital step size signal by one sampling period, c. means for deriving from the delayed digital step size signal a local digital signal, d. an analog step size signal generator responsive to said local digital signal for generating an analog step size signal, e. accumulator means responsive to said digital step size signals for accummulating a digital representation of the sum of the step sizes represented by said digital step size signal, f. a local digital-to-analog converter for converting said accumulated digital representation into a local analog signal, and g. an analog adder for deriving an analog algebraic sum of said local analog signal and said analog step size signal, said analog algebraic sum corresponding to said predicted analog signal.

Claim 3

A converter as claimed in claim 1 wherein said digital step size generator comprises, a. means responsive to first and second patterns of said last received consecutive one-bit pulses for generating a first digital step size signal representing a first predetermined step size, said first pattern comprising four consecutive 1-bit pulses of the same bit value, said second pattern comprising three consecutive 1-bit pulses, including the last received 1-bit pulse, of a first bit value, and four preceding consecutive 1-bit pulses of a second bit value, b. means responsive to third, fourth and fifth patterns of said last received consecutive 1-bit pulses for generating a second digital step size signal representing a second predetermined step size, said third pattern comprising three consecutive 1-bit pulses, including said last received 1-bit pulse, of a first bit value preceded by not more than three consecutive one-bit pulses of a second bit value, said fourth pattern comprising two consecutive 1-bit pulses, including said last received 1-bit pulse, of a first value preceded by four consecutive 1-bit pulses of a second bit value, and said fifth pattern comprising four consecutive bit pulses of a first bit value preceding a last received bit pulse of a second bit value, and c. means responsive to the absence of all of said first through fifth patterns for producing a third digital step size signal representing a third predetermined step size, the ratio of said first to said second to said third predetermined step sizes being 4 : 2 : 1.

Claim 4

A converter as claimed in claim 1, wherein: said at least three step sizes are + or - 2i times a unit step size where i is one of consecutive integers 0, 1, . . . , and n, n being at least two, and said digital step size generator means comprises means for offsetting a preselected one of two step sizes + or - (said unit step size) by an amount given by 1/(2m) of said unit step size where m is a predetermined positive integer.

Claim 5

A converter as claimed in claim 1, wherein said means for deriving said local digital signal comprises, means for deriving a second digital albegraic sum of said digital step size signal and said delayed digital step size signal to produce said local digital signal.

Claim 6

A converter as claimed in claim 1 wherein said self-correlated analog signal substantially periodically assumes a combination of predetermined analog values, said converter further comprising: a predetermined analog value detector responsive to said self-correlated analog signal for producing a detection signal each time said self-correlated analog signal assumes said combination of said predetermined analog values, means responsive to said detection signal for resetting said accumulator means to accumulate therein a prescribed digital value, and a specific code substitution circuit responsive to said detection signal for substituting a specific code into said digital signal in place of the sequence of one-bit pulses which would otherwise occur in said digital signal, said specific code being selected so as never to appear in said one-bit pulse train unless the substitution is carried out.

Claim 7

A converter as claimed in claim 1 wherein said self-correlated analog signal substantially periodically assumes a combination of predetermined analog values, and said one-bit pulse train assumes a combination of predetermined digital values in correspondence to said self-correlated analog signal asssuming each combination of said predetermined analog values, said converter further comprising: a predetermined digital value detector responsive to said one-bit pulse train for producing a detection signal each time said one-bit pulse train assumes the combination of said predetermined digital values, means responsive to said detection signal for resetting said accumulator means to accumulate therein a prescribed digital value, and a specific code substitution circuit responsive to said detection signal for substituting a specific code for each combination of said predetermined digital values, said specific code being representative of the arithmetic means of each combination of said predetermined analog values.

Claim 8

A converter as claimed in claim 1, wherein said accumulator means comprises means for limiting said accumulated digital signal below a predetermined digital signal level, and means for memorizing said accumulated digital signal.

Claim 9

A converter as claimed in claim 1 wherein said accumulator means comprises, a digital storage means adapted to store digital values up to a fixed maximum, digital adder means responsive to said digital step size signals and to the value stored in said storage means for providing a digital algebraic sum, and digital clamping means responsive to said dIgital algebraic sum for providing at its output thereof said digital algebraic sum limited to a maximum value less than said fixed maximum, said last mentioned output being applied to said storage means as said accumulated digital representation.

Claim 10

A converter as claimed in claim 1 wherein said accumulator means comprises a digital storage means adapted to store digital values up to a fixed maximum, digital clamping means responsive to said stored value for providing at its output thereof said stored digital value limited to a maximum value which is more than the maximum digital step size below said fixed maximum of said storage means, and digital adder means for adding the said digital step size signals to said limited stored digital values to produce an accumulated sum which is entered into said digital storage means.