Dial pulse correction circuit for telephone signaling system

Claim 2

A dial pulse correction circuit responsive to received-input dial pulse signals with break and make pulse intervals which are each greater than a first prescribed minimum time interval for producing corRected dial pulse signals with break pulse intervals of at least a second prescribed minimum time interval, comprising: first-control means responsive to transitions of a binary dial pulse input signal for changing the binary logic level of the output thereof; second-timing means normally operating for producing an output of one logic level and being triggered in response to at least certain changes in the output logic level of said first means that are of one polarity to produce an output of another logic level for only a period of time that is equal to the first time interval; third-sample storage means responsive to the change in the output of said second means from the another to the one logic level in going back to its normal operating state for sampling and storing the logic level of the input signal, the logic level stored by said third means being changed only when the logic level of the input signal is the same value at the beginning and at the end of a first time interval over which the output of said second means is the another logic level; fourth-timing means normally operating for producing an output of one logic level and being responsive to a change of one polarity of the logic level stored by said third-storage means for producing an output of another logic level for a period of time that is equal to the second prescribed time interval; and, fifth-control means being responsive to a signal stored by said third means of only one of the binary logic levels for operating to cause the output thereof to be of one logic level, and also being responsive to the another logic level output signal from said fourth-timing means for operating to cause the output thereof to be of the same one logic level; the corrected dial pulse signal being the output signal of said fifth means which is of the one logic level for at least a period of time that is equal to the second time interval.

Claim 3

A dial pulse correction circuit responsive to received-input dial pulse signals with break and make pulse intervals which are each greater than a first prescribed minimum time interval for producing corrected dial pulse signals with break pulse intervals of at least a second prescribed minimum time interval, comprising: first-control means responsive to transitions of a binary dial pulse input signal for changing the binary logic level of the output thereof; second-timing means comprising a first monostable multivibrator normally operating in a stable state for producing an output of one logic level and being triggered during operation in the stable state by at least certain changes in the output logic level of said first means that are of one polarity for operation in a triggered state to produce an output of another logic level for only a period of time that is equal to the first time interval, and is unresponsive during operation thereof in the triggered state to such changes in the output logic level of said first means; third-sample storage means responsive to the change in the output of said second means from the another to the one logic level in going back to its normal operating state for sampling and storing the logic level of the input signal, the logic level stored by said third means being changed only when the logic level of the input signal is the same value at the beginning and at the end of a first time interval over which the output of said second means is the another logic level; fourth-timing means normally operating for producing an output of one logic level and being responsive to a change of one polarity of the logic level stored by said third-storage means for producing an output of another logic level for a period of time that is equal to the second prescribed time interval; and, fifth-control means being responsive to a signal stored by said third means of only one of the binary logic levels for operating to cause the output thereof to be of one logic level, and also being responsive to the another logic level output signal from said fourth-timing means for operating to cause the output thereof to be of the same one logic level; the corrected dial pulse signal being the output signal of said fifth means which is of the one logic level for at least a period of time that is equal to the second prescribed time interval.

Claim 4

A dial pulse correction circuit responsive to received-input dial pulse signals with break and make pulse intervals which are each greater than a first prescribed minimum time interval for producing corrected dial pulse signals with break pulse intervals of at least a second prescribed minimum time interval, comprising: first-control means responsive to transitions of a binary dial pulse input signal for changing the binary logic level of the output thereof; second-timing means comprising a first monostable multivibrator normally operating in a stable state for producing an output of one logic level and being triggered during operation in the stable state by at least certain changes in the output logic level of said first means that are of one polarity for operation in a triggered state to produce an output of another logic level for only a period of time that is equal to the first time interval, and is unresponsive during operation thereof in the triggered state to such changes in the output logic level of said first means; third-sample storage means responsive to the change in the output of said second means from the another to the one logic level in going back to its normal operating state for sampling and storing the logic level of the input signal, the logic level stored by said third means being changed only when the logic level of the input signal is the same value at the beginning and at the end of a first time interval over which the output of said second means is the another logic level; fourth-timing means normally operating for producing an output of one logic level and being responsive to a change of one polarity of the logic level stored by said third-storage means for producing an output of another logic level for a period of time that is equal to the second prescribed time interval; and, fifth-control means being responsive to a signal stored by said third means of only one of the binary logic levels for operating to cause the output thereof to be of one logic level, and also being responsive to the another logic level output signal from said fourth-timing means for operating to cause the output thereof to be of the same one logic level; the corrected dial pulse signal being the output signal of said fifth means which is of the one logic level for at least a period of time that is equal to the second prescribed time interval.

Claim 5

The correction circuit according to claim 2 wherein said fourth-timing means comprises a second monostable multivibrator circuit that is responsive during operation thereof in a stable state to changes in the logic level stored by said third means that are of the one polarity for operating in a triggered state for a time period that is equal to the second time interval, and is unresponsive during operation thereof in the triggered state to such changes in the logic level stored by said third means.

Claim 6

The correction circuit according to claim 3 wherein said first-control means is responsive to logic levels stored by said third-storage means and to input dial pulses for changing the binary logic level output thereof on each transition of a binary dial pulse input signal.

Claim 7

The correction circuit according to claim 4 wherein said third means comprises a bistable multivibrator circuit which is clocked only on termination of operation of said first monostable multivibrator circuit in the triggered state for being responsive to the input dial pulse signal so that the latter signal controls the stable state of said bistable circuit.

Claim 8

The correction circuit according to claim 5 wherein said first-control means comprises an EXCLUSIVE-OR gate circuit.

Claim 9

The correction circuit according to claim 6 wherein said fifth means comprises a NOR-gate logic circuit.

Claim 10

The correction circuit according to claim 7 wherein said monostable multivibrator circuits have clear terminals and said bistable multivibrator circuit has clear and preset terminals; and including sixth means connecting high logic level one''s to said clear and preset terminals.

Claim 11

A dial pulse correction circuit responsive to received-input dial pulse signals with break and make pulse intervals which are each greater than a first prescribed minimum time interval for producing corrected dial pulse signals with break pulse intervals of at least a second prescribed minimum time interval, comprising: first-control means responsive to binary dial pulse input signals and operative for changing the binary logic level of the output thereof for each transition of the input dial pulse; second-timing means normally operating in a stable logic state and being responsive during operation thereof in the stable state to changes in the output logic level of said first means that are of only one polarity for operating in a triggered state for only a time period that is equal to the first time interval; third-sample storage means responsive to termination of operation of said second means in the triggered state for sampling and storing the logic level of the input signal, the logic level stored by said third means being changed only when the logic level of the input signal is the same value at the beginning and at the end of a first time interval over which said second means operates in the triggered state; fourth-timing means normally operating in a stable logic state and being responsive during operation thereof in the stable state to a change of one polarity of the logic level of the signal stored by said third means for operating in a triggered-monostable state for only a time period that is equal to the second prescribed time interval; and, fifth-control means being responsive to a signal stored by said third means and of only one of the two binary logic levels for operating to cause the output thereof to be of one logic level, and also being responsive to operation of said fourth timing means in the triggered state for operating to cause the output thereof to be of the same one logic level; the corrected dial pulse signal being the output signal of said fifth means which is of the one logic lEvel for at least a period of time that is equal to the second prescribed time interval.

Claim 12

A dial pulse correction circuit responsive to received-input dial pulse signals with break and make pulse intervals which are each greater than a first prescribed minimum time interval for producing corrected dial pulse signals with break pulse intervals of at least a second prescribed minimum time interval, comprising: first-control means responsive to binary dial pulse input signals and operative for changing the binary logic level of the output thereof for each transition of the input dial pulse; second-timing means normally operating in a stable logic state and being responsive during operation thereof in the stable state to changes in the output logic level of said first means that are of only one polarity for operating in a triggered state for only a time period that is equal to the first time interval; third-sample storage means responsive to termination of operation of said second means in the triggered state for sampling and storing the logic level of the input signal, the logic level stored by said third means being changed only when the logic level of the input signal is the same value at the beginning and at the end of a first time interval over which said second means operates in the triggered state; fourth-timing means normally operating in a stable logic state and being responsive during operation thereof in the stable state to a change of one polarity of the logic level of the signal stored by said third means for operating in a triggered-monostable state for only a time period that is equal to the second prescribed time interval; and, fifth-control means being responsive to a signal stored by said third means and of only one of the two binary logic levels for operating to cause the output thereof to be of one logic level, and also being responsive to operation of said fourth timing means in the triggered state for operating to cause the output thereof to be of the same one logic level; the corrected dial pulse signal being the output signal of said fifth means which is of the one logic lEvel for at least a period of time that is equal to the second prescribed time interval.