US3671875A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digitally operated signal regenerator and timing circuit
Assignee: AT&T Inc
•
Filing: 1971-05-20
•
Granted: 1972-06-20
•
Expires: 1991-05-20
Abstract
Abstract A digitally operated signal timing circuit employs a single synchronous up-down counter with overriding set and reset in combination with a group of flip-flops and logic gates. In effecting the regeneration of input pulses, such as the pulses produced by a telephone dial, a plurality of signal timing functions are provided by the combination indicated, which functions include the establishment of an operate threshold delay, a release delay, a minimum output pulse duration, a minimum duration interval between pulses and an idle condition holdover period.
Inventors
- 👤 Frank Louis Pento
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 21:03
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/156; H03K5/13; H03K5/135; H04; H04Q; H04Q1/00; H04Q1/18; H04Q1/30; H04Q1/32; H04Q1/36
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
69 words
A multifunction pulse regeneration circuit employing only a single digital timer comprising, in combination, first means including said timer for establishing an operate threshold delay, second means including saId timer for establishing a release delay, third means including said timer for establishing a minimum break duration, fourth means including said timer for establishing a minimum make duration, and fifth means including said timer for establishing an idle condition holdover.
Claim 2
Dependent Claim
69 words
A multifunction pulse regeneration circuit employing only a single digital timer comprising, in combination, first means including said timer for establishing an operate threshold delay, second means including saId timer for establishing a release delay, third means including said timer for establishing a minimum break duration, fourth means including said timer for establishing a minimum make duration, and fifth means including said timer for establishing an idle condition holdover.
Claim 3
Dependent Claim
19 words
Apparatus in accordance with claim 1 wherein said timer comprises a synchronous up-down counter with overriding set and reset.
Claim 4
Dependent Claim
16 words
Apparatus in accordance with claim 2 including means for applying a clock signal to said timer.
Claim 5
Dependent Claim
54 words
Apparatus in accordance with claim 3 wherein each of said first, second, third, fourth and fifth means further includes a plurality of logic gates and flip-flops, input points, output points, means interconnecting said points by way of said clock, said gates and said flip-flops and means for applying said clock signal to said timer.
Claim 6
Dependent Claim
19 words
Apparatus in accordance with claim 4 wherein each of said gates comprises a NAND gate having a complementary output.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-06-20 | 1975-12-20 | 1976-06-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-06-20 | 1979-12-20 | 1980-06-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-06-20 | 1983-12-20 | 1984-06-20 | $7700.00 | Window Closed / Lapsed |