Odd-sized memory having a plurality of even-sized storage elements of the same capacity

Claim 2

A memory for storing a plurality of individually addressable words, each word having at least one word segment, wherein each word segment of each of the words is stored in a different one of a plurality of distinct storage elemeNts, the elements being separated into a first group of storage elements and a second group of storage elements, and wherein each of the storage locations for a word is identified for access by a memory address signal having at least as many possible states as the number of words to be accessed, the memory address signal having an expansion address signal component thereof having a first state and a second state; which memory comprises: a. means for accessing the first group of storage elements when the expansion address signal is in its first state only; and b. means for accessing less than all of the storage locations in the second group of storage elements when the expansion adress signal is in its first state.

Claim 3

A memory as recited in claim 1 which comprises means for accessing only the second group of storage elements when the expansion address signal is in its second state.

Claim 4

An odd-sized memory for storing at least W individually addressable words, each word comprising a plurality of word segments, where W is an integer greater than 2M but less than 2M 1 and where M is an integer greater than zero, which comprises: a. means for generating an expansion address signal having a first state and a second state; b. means for generating a row address signal having at least 2N possible states, N being an integer greater than zero but no greater than M; c. at least two storage elements each having a plurality of individually addressable storage locations for word segments, each of said storage elements having addressing means operatively associated therewith for responding to an element address signal supplied thereto to identify a storage location therein for access, each of said storage elements further having enabling means operatively associated therewith for enabling access to an identified storage location in response to an enabling signal supplied thereto; d. means for supplying an element address signal having 2M possible states to said storage elements when the expansion address signal is in its first state; e. first means for supplying an enabling signal to a first one of said storage elements when the expansion address signal is in its first state; and f. second means for supplying an enabling signal to a second one of said storage elements when the expansion address signal is in its first state and when the row address signal is in certain selected states, fewer than 2N in number, whereby some, but not all, of the storage locations in said second storage element are selected to be unavailable for access when the expansion address signal is in its first state.

Claim 5

An odd-sized memory for storing at least W individually addressable words, each word comprising a plurality of word segments, where W is an integer greater than 2M but less than 2M 1 and where M is an integer greater than zero, which comprises: a. means for generating an expansion address signal having a first state and a second state; b. means for generating a row address signal having at least 2N possible states, N being an integer greater than zero but no greater than M; c. at least two storage elements each having a plurality of individually addressable storage locations for word segments, each of said storage elements having addressing means operatively associated therewith for responding to an element address signal supplied thereto to identify a storage location therein for access, each of said storage elements further having enabling means operatively associated therewith for enabling access to an identified storage location in response to an enabling signal supplied thereto; d. means for supplying an element address signal having 2M possible states to said storage elements when the expansion address signal is in its first state; e. first means for supplying an enabling signal to a first one of said storage elements when the expansion address signal is in its first state; and f. second means for supplying an enabling signal to a second one of said storage elements when the expansion address signal is in its first state and when the row address signal is in certain selected states, fewer than 2N in number, whereby some, but not all, of the storage locations in said second storage element are selected to be unavailable for access when the expansion address signal is in its first state.

Claim 6

An odd-sized memory as recited in claim 3, the memory having a memory address signal supplied thereto to identify a particular word for access, wherein said means for generating an expansion address signal is responsive to the memory address signal.

Claim 7

An odd-sized memory as recited in claim 3, the memory having a memory address signal supplied thereto to identify a particular word for access, wherein said means for generating a row address signal is responsive to the memory address signal.

Claim 8

An odd-sized memory as recited in claim 3, the memory having a memory address signal supplied thereto to identify a particular word for access, wherein said means for generating an element address signal is responsive to the memory address signal.

Claim 9

An odd-sized memory as recited in claim 3, wherein said first means for supplying an enabling signal is responsive to the expansion address signal.

Claim 10

An odd-sized memory as recited in claim 3, wherein said second means for supplying an enabling signal is responsive jointly to the expansion address signal and the row address signal.

Claim 11

An odd-sized memory as recited in claim 3, which comprises means for supplying a synthesized element address signal to said second storage element when the expansion address signal is in its second statE, the synthesized element address signal being effective to identify for access only those storage locations selected to be unavailable when the expansion address signal is in its first state.

Claim 12

An odd-sized memory as recited in claim 9 wherein said means for supplying a synthesized element address signal to said second storage element is responsive jointly to the expansion address signal and the row address signal.

Claim 13

An odd-sized memory as recited in claim 3 which comprises means for supplying a synthesized element address signal to said second storage element when the expansion address signal is in its second state, the synthesized element address signal having 2M possible states but being restricted to assume only those states which are effective to identify for access those storage locations selected to be unavailable when the expansion address signal is in its first state.

Claim 14

An odd-sized memory as recited in claim 11 wherein said means for supplying a synthesized element address signal to said second storage element is responsive jointly to the expansion address signal and the row address signal.

Claim 15

An odd-sized memory as recited in claim 3 wherein said storage elements each have word segment signal output means operatively associated therewith for producing a word segment output signal from an identified storage location therein, the word segment output signal appearing at the signal output means of a particular storage element only when that storage element has its enabling signal supplied thereto, the odd-sized memory comprising gate means coupled to the signal output means of said first and second storage elements for transmitting either the word segment output signal of said first storage element or the word segment output signal of said second storage element to the memory output means of the complete odd-sized memory.

Claim 16

An odd-sized memory as recited in claim 13 wherein said gate means comprises OR gate means for transmitting the word segment output signal of said first storage element to the memory output means when said second storage element is not enabled for access and for transmitting the word segment output signal of said second storage element to the memory output means when said second storage element is enabled for access.

Claim 17

An odd-sized memory as recited in claim 14 wherein said gate means comprises a demultiplexer logic circuit, said demultiplexer having a plurality of output circuits for transmitting word segment output signals, said first one of the demultiplexer output circuits being coupled to said OR gate means, said demultiplexer also having the row address signal coupled to decoder circuits therein for selecting the first of the demultiplexer output circuits to be activated for the transmission of a word segment output signal when said second storage element is not enabled for access, said demultiplexer further having the word segment output signal of said first storage element coupled to signal input circuits thereof for transmission to the selected demultiplexer output circuits when the expansion address signal is in its first state.

Claim 18

An improved memory for storing at least W individually addressable words, where W is an integer greater than 2M but less than 2M 1 and where M is an integer greater than zero, the memory having a memory address signal supplied thereto to identify a particular word for access, the memory address signal having at least 2M 1 possible states, the memory being of the type wherein a plurality of physically distinct storage elements are operatively interconnected, each storage element having a plurality of individually addressable storage locations for segments of words, each storage element also having element addressing means associated therewith for identifying a particular storage location for access in response to an element address signal supplied thereto and each storage element further having enabling means assOciated therewith for enabling access to an identified storage location in response to an enabling signal supplied thereto, wherein the improvement comprises: a. means responsive to the memory address signal for generating an expansion address signal having a first possible state and a second possible state; b. means responsive to the memory address signal for generating a row address signal having at least 2N possible states, N being an integer greater than zero but no greater than M; c. means responsive to the memory address signal for supplying an element address signal having 2M possible states to a first storage element and to a second storage element when the expansion address signal is in its first state; d. means responsive to the expansion address signal for supplying an enabling signal to the first storage element when the expansion address signal is in its first state; and e. means responsive jointly to the expansion address signal and the row address signal for supplying an enabling signal to the second storage element when the expansion address signal is in its first state and when the row address signal is in certain selected states, fewer than 2N in number, whereby some, but not all, of the storage locations in the second storage element are selected to be unavailable for access when the expansion address signal is in its first state.

Claim 19

An improved memory for storing at least W individually addressable words, where W is an integer greater than 2M but less than 2M 1 and where M is an integer greater than zero, the memory having a memory address signal supplied thereto to identify a particular word for access, the memory address signal having at least 2M 1 possible states, the memory being of the type wherein a plurality of physically distinct storage elements are operatively interconnected, each storage element having a plurality of individually addressable storage locations for segments of words, each storage element also having element addressing means associated therewith for identifying a particular storage location for access in response to an element address signal supplied thereto and each storage element further having enabling means assOciated therewith for enabling access to an identified storage location in response to an enabling signal supplied thereto, wherein the improvement comprises: a. means responsive to the memory address signal for generating an expansion address signal having a first possible state and a second possible state; b. means responsive to the memory address signal for generating a row address signal having at least 2N possible states, N being an integer greater than zero but no greater than M; c. means responsive to the memory address signal for supplying an element address signal having 2M possible states to a first storage element and to a second storage element when the expansion address signal is in its first state; d. means responsive to the expansion address signal for supplying an enabling signal to the first storage element when the expansion address signal is in its first state; and e. means responsive jointly to the expansion address signal and the row address signal for supplying an enabling signal to the second storage element when the expansion address signal is in its first state and when the row address signal is in certain selected states, fewer than 2N in number, whereby some, but not all, of the storage locations in the second storage element are selected to be unavailable for access when the expansion address signal is in its first state.

Claim 20

An improved memory as recited in claim 16 wherein the improvement comprises means responsive jointly to the expansion address signal and the row address signal for supplying a synthesized element address signal to the second storage element when the expansion address signal is in its second state, the synthesized element address signal being effective to identify for access only those storage locations selected to be unavailable when the expansion address signal is in its first state.

Claim 21

An improved memory as recited in claim 16 wherein the improvement comprises means responsive jointly to the expansion address signal and the row address signal for supplying a synthesized element address signal to the second storage element when the expansion address signal is in its second state, the synthesized element address signal having 2M possible state but being restricted to assume only those states which are effective to identify for access those storage locations selected to be unavailable when said expansion address signal is in its first state.

Claim 22

An improved memory as recited in claim 16 wherein the first and second storage elements each have word segment signal output means operatively associated therewith for producing a word segment output signal from an identified storage location therein, the word segment output signal appearing at the signal output means of a particular storage element only when that storage element has its enabling signal supplied thereto, the improvement comprising gate means coupled to the signal output means of the first and second storage elements for transmitting either the word segment output signal of the first storage element or the word segment output signal of the second storage element to the memory output means of the complete odd-sized memory.

Claim 23

An improved memory as recited in claim 19 wherein said gate means comprises OR gate means for transmitting the word segment output signal of the first storage element to the memory output means when the second storage element is not enabled for access and for transmitting the word segment output signal of the second storage element to the memory output means when the second storage element is enabled for access.

Claim 24

An odd-sized memory as recited in claim 20 wherein said gate means comprises a demultiplexer logic circuit, said demultiplexer having a plurality of output circuits for transmitting word segment output signals, a first one of the demultiplexer output circuits being coupled to said OR gate means, said demultiplexer also having the row address signal coupled to decoder circuits therein for selecting the first of the demultiplexer output circuits to be activated for the transmission of a word segment output signal when the second storage element is not enabled for access, said demultiplexer further having the word segment output signal of the first storage element coupled to signal input circuits thereof for transmission to the selected demultiplexer output circuits when the expansion address signal is in its first state.

Claim 25

An odd-sized memory for storing at least W individually addressable words, where W is an integer greater than 2M but less than 2M 1 and M is an integer greater than zero, the memory comprising word segment storage locations mapped onto a graphic array of rows and columns, the array having at least 2N rows in a base array portion thereof, N being an integer greater than zero but no greater than M, the array also having at least one row in an expansion array portion thereof, the odd-sized memory comprising, in combination: a. means for generating a memory address signal having at least 2M 1 possible states, the memory address signal comprising an expansion address signal having a first state associated with mapping selected storage locations onto the base array portion and a second state associated with mapping other selected storage locations onto the expansion array portion, the memory address signal also comprising a row address signal having at least 2N possible states each distinct one of which is associated with mapping selected groups of storage locations onto corresponding distinct rows of the base array portion; b. at least K+1 storage elements each having a plurality of individually addressable storage locations therein for word segments, K being equal to the number of word segments comprising a word, each of said storage elements having addressing means operatively associated therewith for responding to an element address signal supplied thereto for identifying a particular one of the storage locations therein for access, each of said storage elements also having enabling means operatively associated therewith for responding to an enabling signal supplied thereto for allowing access to the identified storage location, said storage elements being divided into a first group of at least K base storage elements and a second group of at least one expansion storage element; c. means for supplying the same base array element address signal to all of said storage elements when the expansion address signal is in its first state, the base array element address signal having the row address signal as a component thereof whereby the storage locations of each of said storage elements are, in effect, divided by the row address signal into at least 2N groups, one distinct group for each of the possible states of the row address signal; d. means responsive to the row address signal, when the expansion address is in its first state, for selectively applying an enabling signal to said base storage elements for at least one but less than all of the possible states of the row address signal whereby at least one group of storage locations in each of said base storage elements is reserved for mapping onto the expansion array portion; and e. means responsive to the expansion address signal for supplying an enabling signal to each expansion storage element whenever the expansion address signal is in its first state only whereby the storage locations in expansion storage elements are reserved for mapping onto the base array portion.

Claim 26

An odd-sized memory for storing at least W individually addressable words, where W is an integer greater than 2M but less than 2M 1 and M is an integer greater than zero, the memory comprising word segment storage locations mapped onto a graphic array of rows and columns, the array having at least 2N rows in a base array portion thereof, N being an integer greater than zero but no greater than M, the array also having at least one row in an expansion array portion thereof, the odd-sized memory comprising, in combination: a. means for generating a memory address signal having at least 2M 1 possible states, the memory address signal comprising an expansion address signal having a first state associated with mapping selected storage locations onto the base array portion and a second state associated with mapping other selected storage locations onto the expansion array portion, the memory address signal also comprising a row address signal having at least 2N possible states each distinct one of which is associated with mapping selected groups of storage locations onto corresponding distinct rows of the base array portion; b. at least K+1 storage elements each having a plurality of individually addressable storage locations therein for word segments, K being equal to the number of word segments comprising a word, each of said storage elements having addressing means operatively associated therewith for responding to an element address signal supplied thereto for identifying a particular one of the storage locations therein for access, each of said storage elements also having enabling means operatively associated therewith for responding to an enabling signal supplied thereto for allowing access to the identified storage location, said storage elements being divided into a first group of at least K base storage elements and a second group of at least one expansion storage element; c. means for supplying the same base array element address signal to all of said storage elements when the expansion address signal is in its first state, the base array element address signal having the row address signal as a component thereof whereby the storage locations of each of said storage elements are, in effect, divided by the row address signal into at least 2N groups, one distinct group for each of the possible states of the row address signal; d. means responsive to the row address signal, when the expansion address is in its first state, for selectively applying an enabling signal to said base storage elements for at least one but less than all of the possible states of the row address signal whereby at least one group of storage locations in each of said base storage elements is reserved for mapping onto the expansion array portion; and e. means responsive to the expansion address signal for supplying an enabling signal to each expansion storage element whenever the expansion address signal is in its first state only whereby the storage locations in expansion storage elements are reserved for mapping onto the base array portion.

Claim 27

An odd-sized memory as recited in claim 22 which comprises means responsive to the row address signal and the expansion address signal jointly, when the expansion address is in its second state, for supplying both an enabling signal and an expansion array element address signal to each base storage element, each of the expansion array element addreSs signals having a synthesized row address portion adapted to cause the reserved group of storage locations in each of said base storage elements to be mapped onto the expansion array portion.

Claim 28

An odd-sized memory as recited in claim 22 wherein the means for reading a word out of the memory comprises gate means responsive jointly to the expansion address signal and the row address signal for reading out at least one word segment of the word from an expansion storage element when the expansion address signal is in its first state and reading out all word segments of the word from base storage elements when the expansion address signal is in its second state.

Claim 29

A Class N odd-sized memory section for storing segments of at least W individually addressable words, W being an integer greater than 2M but less than 2M 1, M being an integer greater than zero, and N being an integer greater than zero but no greater than M; wherein the memory section is organized for addressing into an array of R rows and C columns, R being equal to 2N+1 and C being an integer greater than zero but no greater than 2N, each column having a word segment in each individually addressable location thereof and each row having 2M N individually addressable locations of length C word segments each; and wherein the array is partitioned into a base array portion comprising 2N of the rows and an expansion array portion comprising the remaining row not included in the base array portion; the memory section comprising, in combination: a. means for generating a memory address signal for the memory section wherein the memory address signal has a length of M+1 bits partitioned into a common address signal comprising the MN least significant bits thereof, an expansion address signal comprising the most significant bit thereof, and a row address signal comprising the N bits thereof intermediate the most significant bit and the M-N least significant bits, wherein the expansion address signal has a first state effective for selecting the addressable locations of the base array portion for access and a second state effective for selecting the addressable locations of the expansion array portion for access, and wherein the row address signal has 2N possible states, each one of which is effective for selecting a different one of the rows of the base array portion for access; b. C+1 storage elements each having 2M individually addressable storage locations for word segments therein, each storage element also having addressing means operatively associated therewith for responding to an M-bit element address signal supplied thereto to identify a storage location for access, and each storage element further having enabling means operatively associated therewith for responding to an enabling signal applied thereto to enable access to an identified storage location, said storage elements being grouped into a first set comprising C base storage elements, each one of which is reserved for storing word segments associated with a different specific column of the array, and a second set comprising one expansion storage element; c. means responsive to the expansion address signal for supplying an enabling signal to said expansion storage element only when the expansion address signal is in its first state whereby said expansion storage element is reserved for storing word segments situated in the base array portion; d. means responsive jointly to the expansion address signal and the row address signal for supplying an enabling signal to each one of said base storage elements when the expansion address signal is in its first state for all but one selected one of the 2N possible states of the row address signal, a different state of the row address signal being selected to be effective for the absence of the enabling signal for each diffeRent one of said base storage elements whereby each base storage element has 2M N storage locations therein selected to be unavailable for access when the expansion address signal is in its first state; and e. means for supplying an M-bit element address signal to said storage elements wherein the element address signal comprises the common address signal for the M-N least significant bits thereof and the row address signal for the N most significant bits thereof when the expansion address signal is in its first state.

Claim 30

A Class N odd-sized memory section for storing segments of at least W individually addressable words, W being an integer greater than 2M but less than 2M 1, M being an integer greater than zero, and N being an integer greater than zero but no greater than M; wherein the memory section is organized for addressing into an array of R rows and C columns, R being equal to 2N+1 and C being an integer greater than zero but no greater than 2N, each column having a word segment in each individually addressable location thereof and each row having 2M N individually addressable locations of length C word segments each; and wherein the array is partitioned into a base array portion comprising 2N of the rows and an expansion array portion comprising the remaining row not included in the base array portion; the memory section comprising, in combination: a. means for generating a memory address signal for the memory section wherein the memory address signal has a length of M+1 bits partitioned into a common address signal comprising the MN least significant bits thereof, an expansion address signal comprising the most significant bit thereof, and a row address signal comprising the N bits thereof intermediate the most significant bit and the M-N least significant bits, wherein the expansion address signal has a first state effective for selecting the addressable locations of the base array portion for access and a second state effective for selecting the addressable locations of the expansion array portion for access, and wherein the row address signal has 2N possible states, each one of which is effective for selecting a different one of the rows of the base array portion for access; b. C+1 storage elements each having 2M individually addressable storage locations for word segments therein, each storage element also having addressing means operatively associated therewith for responding to an M-bit element address signal supplied thereto to identify a storage location for access, and each storage element further having enabling means operatively associated therewith for responding to an enabling signal applied thereto to enable access to an identified storage location, said storage elements being grouped into a first set comprising C base storage elements, each one of which is reserved for storing word segments associated with a different specific column of the array, and a second set comprising one expansion storage element; c. means responsive to the expansion address signal for supplying an enabling signal to said expansion storage element only when the expansion address signal is in its first state whereby said expansion storage element is reserved for storing word segments situated in the base array portion; d. means responsive jointly to the expansion address signal and the row address signal for supplying an enabling signal to each one of said base storage elements when the expansion address signal is in its first state for all but one selected one of the 2N possible states of the row address signal, a different state of the row address signal being selected to be effective for the absence of the enabling signal for each diffeRent one of said base storage elements whereby each base storage element has 2M N storage locations therein selected to be unavailable for access when the expansion address signal is in its first state; and e. means for supplying an M-bit element address signal to said storage elements wherein the element address signal comprises the common address signal for the M-N least significant bits thereof and the row address signal for the N most significant bits thereof when the expansion address signal is in its first state.

Claim 31

A class N odd-sized memory section as recited in claim 25 which comprises means for supplying a different M-bit element address signal to each distinct one of said base storage elements when the expansion address signal is in its second state wherein each of the different element address signals comprises the common address signal for the M-N least significant bits thereof and, for the N most significant bits thereof, a signal having that selected row address signal state for each of said base storage elements for which no enabling signal is supplied when the expansion address is in its first state.

Claim 32

A class N odd-sized memory section as recited in claim 25 wherein the means for reading a word out of the memory comprises gate means responsive jointly to the expansion address signal and the row address signal for reading out at least one word segment of the word from an expansion storage element when the expansion address signal is in its first state and reading out all word segments of the word from base storage elements when the expansion address signal is in its second state.

Claim 35

A method of accessing a memory as recited in claim 28 which comprises accessing only the second group of storage elements when the expansion address signal is in its second state.

Claim 38

A method of addressing a memory as recited in claim 30 which comprises: a. generating a synthesized row address signal having at least 2N possible states but restricted to having only the selected row address signal states; b. supplying an element address signal comprising the common address signal and the synthesized row address signal to the base storage element when the expansion address signal is in its second state; and c. supplying an enabling signal to the base storage element when the expansion address signal is in its second state.