General purpose associative processor

Claim 1

A solid state, variable syllable, variable instruction, associative processor which comprises, a plurality of identical associative chip elements each containing an integral number of associative memory bits, a plurality of identical, vertically stacked associative processor words, said plurality of words determining any desired processor size, said words comprising a plurality of identical associative chip elements, each of said elements horizontally connected to adjacent chip elements, said plurality of horizontally connected chip elements determining any desired word size, a write bus for each word connected to each associative chip element of the word for controlling the writing of information into that word, an add bus for each word connected to each associative chip element of the word for controlling add functions within that word, a response store comprising a plurality of memory flip-flops, and for each processor word, said response store section connected to one end of its associated processor word and to the add bus and write bus of that word, said response store section simultaneously controlling each word in the parallel processing of data stored within each processor word, controlling various search operations performed simultaneously within each processor word, and stores the results of these search operations, a plurality of control flip-flop registers equal in width to the combined width of the processor word and the response store, each bit of each of said registers connected in parallel to the corresponding bit in every processor word and its response store section, said control registers defining syllable limits to be observed in any operation, specifying which syllables will participate in the various search, logical, write, multi-write, and multiadd operations, specifying the type of search for each syllable when a search operation is performed, receives data outputs from any processor word, receives data from and provides data to any device which may be using the processor, and provides data inputs to the processor, said data inputs are compared in one step and under various criteria specified by the control registers to data stored within every processor word, the results of said comparisons being stored in the response store, whereby said data inputs are in one step written into one or more processor words or portions of one or more processor words, and in one step combined with data in one or more processor words in arithmetic and logical operations, the results of said operations being stored within the processor words, and said read, write, multi-write, add, multi-add, and logical operations are each performed in only one step and combinations of said operations performed simultaneously.