Alphanumeric terminal for a communications system

Claim 2

In a communications system utilizing digitally encoded messages and including a transmitter and receiver, a terminal with the capability of sending predetermined messages comprising: a. keyboard means providing text signals representative of alphanumeric characters and control signals in response to operation of keys thereon; b. a text memory connected to receive and store the text signals from said keyboard means; c. a fixed message memory having therein predetermined messages and connected to receive control signals from said keyboard means for selecting predetermined messages therein in response to operation of control keys on said keyboard means; d. an address memory having therein an address code of said transmitter and receiver; e. logic circuitry connected to receive the text signals from said text memory, the selected predetermined messages from said fixed message memory and the address code from said address memory and providing a first digital message serially including the text signals, the selected predetermined messages and the address code; f. a parity generator and interleaving circuit connected to receive the first digital message from said logic circuitry and periodically generate and insert parity bits therein, said parity generator and interleaving circuit developing a second digital message serially including the text signals, the selected predetermined messages, the address code and the parity bits and interleaving the first and second digital messages into a composite message; and g. means connecting the composite message to said transmitter.

Claim 3

A communications system as claimed in claim 1 including a psuedo random code generator connected to the connecting means and providing a pseudo random code serialLy preceding the composite message.

Claim 4

A communications system as claimed in claim 2 wherein the pseudo random code generator includes circuitry for providing several pseudo random codes each of which is an indication of the type of message to follow.

Claim 5

A communications system as claimed in claim 1 wherein the connecting means includes an encoder and modulator for differentially encoding the composite signal and modulating the differentially encoded signal at a predetermined frequency.

Claim 6

A communications system as claimed in claim 1 wherein the parity generator and interleaving circuit includes delay means for delaying the second digital message for a short period relative to the first digital message prior to interleaving the two messages.

Claim 7

A communications system as claimed in claim 1 wherein the logic circuitry includes means for inserting the address code twice in each of the first and second digital messages.

Claim 8

A communications system as claimed in claim 6 wherein the logic circuit and the parity generator and interleaving circuit are connected to provide each of the first and second digital messages in the following form, the address code, followed by a repeat of the address code, followed by at least one predetermined message, followed by any signals stored in the data memory, and followed by a stop indicating signal.

Claim 9

A communications system as claimed in claim 7 wherein the fixed message memory includes an acknowledge memory and an acknowledge code is serially included in the first digital message by said logic circuitry.

Claim 10

A communications system as claimed in claim 8 wherein the parity generator and interleaving circuit, the acknowledge memory, the address memory and the fixed message memory are all constructed so that the first and second digital messages each are serially composed of a first portion having a fixed length including a 16 bit address, a repeated 16 bit address, a first four bit predetermined message, a second four bit predetermined message and a two bit acknowledgment code and a second text portion variable in length with both the fixed and variable portions having a parity bit inserted after every sixth information bit.

Claim 11

A communications system as claimed in claim 9 wherein the pseudo random generator is constructed to provide approximately 127 bits serially preceding the first address.

Claim 12

A communications system utilizing digitally encoded messages comprising: a. a base station including a transmitter, a receiver and means for processing messages; and b. a plurality of mobile stations each including a transmitter and receiver and a terminal including keyboard means providing text signals representative of alphanumeric characters and control signals in response to operation of keys thereon, a text memory connected to receive and store the text signals from said keyboard means, a fixed message memory having therein predetermined messages and connected to receive control signals from said keyboard means for selecting predetermined messages therein in response to operation of control keys on said keyboard means, an address memory having therein an address code of said mobile transmitter and receiver, logic circuitry connected to receive the text signals from said text memory, the selected predetermined messages from said fixed message memory and the address code from said address memory and providing a first digital message serially including the text signals, the selected predetermined messages and the address code, a parity generator and interleaving circuit connected to receive the first digital message from said logic circuitry and periodically generate and insert parity bits therein, said parity generator and interleaving circuit developing a second digital message serially including the text signals, the selected predetermined messages, the address code and the parity bits and interleaving the first and second digital messages into a composite message, means connecting the composite message to said transmitter of the associated mobile station, signal processing circuitry connected to said associated mobile receiver and said logic circuitry for converting received signals including interleaved first and second messages into a usable message, comparing means connected to said logic circuitry and said address memory for identifying messages received by said associated mobile receiver which contain the address code thereof, and display means connected to said logic circuitry for displaying text messages supplied to said text memory and for displaying messages identified by said comparing means.

Claim 13

A communications system utilizing digitally encoded messages comprising: a. a base station including a transmitter, a receiver and means for processing messages; and b. a plurality of mobile stations each including a transmitter and receiver and a terminal including keyboard means providing text signals representative of alphanumeric characters and control signals in response to operation of keys thereon, a text memory connected to receive and store the text signals from said keyboard means, a fixed message memory having therein predetermined messages and connected to receive control signals from said keyboard means for selecting predetermined messages therein in response to operation of control keys on said keyboard means, an address memory having therein an address code of said mobile transmitter and receiver, logic circuitry connected to receive the text signals from said text memory, the selected predetermined messages from said fixed message memory and the address code from said address memory and providing a first digital message serially including the text signals, the selected predetermined messages and the address code, a parity generator and interleaving circuit connected to receive the first digital message from said logic circuitry and periodically generate and insert parity bits therein, said parity generator and interleaving circuit developing a second digital message serially including the text signals, the selected predetermined messages, the address code and the parity bits and interleaving the first and second digital messages into a composite message, means connecting the composite message to said transmitter of the associated mobile station, signal processing circuitry connected to said associated mobile receiver and said logic circuitry for converting received signals including interleaved first and second messages into a usable message, comparing means connected to said logic circuitry and said address memory for identifying messages received by said associated mobile receiver which contain the address code thereof, and display means connected to said logic circuitry for displaying text messages supplied to said text memory and for displaying messages identified by said comparing means.

Claim 14

A communications system utilizing digitally encoded messages as claimed in claim 11 wherein the signal processing circuitry includes parity checking means supplying an output signal indicative of an error in the portion of the received signal associated with each of the parity bits checked and gating means connected to receive the output signal and connect the portions of one of the first and second messages in the received signal which do not contain errors to said logic circuitry.

Claim 15

A communications system utilizing digitally encoded messages as claimed in claim 11 wherein the signal processing circuit includes noise indication means for comparing the amplitude of each bit in the received signal to predetermined high and low levels and providing output signals indicating bits not exceeding said levels, and gating means connected to receive the output signals and connect the bits of one of the first and second messages in the received signal which exceed said levels to said logic circuitry.

Claim 16

A communications system utilizing digitally encoded messages as claimed in claim 13 wherein the signal processing circuit includes means for separating the first and second messages in the received signal and means for matching each word in the first message to the words in the second message representing the same portion of the message, said matching means providing an output signal indicative of matches, the output signal of said matching means being supplied to said gating means and operating said gating means to connect the words of one of the first and second messages in the received signal to said logic circuitry when a match is indicated.

Claim 17

In a communication system including a receiver for receiving a signal composed of a first digital message interleaved with a second digital message, which is the first digital message repeated, and periodic parity bits, signal processing circuitry comprising: a. parity checking means having applied thereto the received signal and providing an output signal indicative of an error in the portion of the received signal associated with each of the parity bits checked; b. noise indication means having applied thereto the received signal for comparing the amplitude of each bit in the received signal to predetermined high and low levels and providing output signals indicating bits not exceeding said levels; c. separating means having applied thereto the received signal and separating the first and second messages therein; d. matching means connected to said separating means and matching each word in the first message to each word in the second message, said matching means providing an output signal indicative of matching words; and e. gating means connected to receive the output signals from said parity checking means, said noise indication means and said matching means, said gating means including circuitry for passing digital words in one of said first and second messages which do not have parity errors and which contain bits that exceed the high and low levels of the noise indication means, said gating means further including circuitry for passing digital words in one of said first and second messages which do not have parity errors, which contain bits that do not exceed the high and low levels of the noise indication means and which match, and said Gating means further including circuitry providing a flag signal when the same digital word in both the first and second messages contains one of a parity error, a parity error and bits which do not exceed the levels in the noise indication means, and a mismatch and bits which do not exceed the levels in the noise indication means.

Claim 18

In a communication system including a receiver for receiving a signal composed of a first digital message interleaved with a second digital message, which is the first digital message repeated, and periodic parity bits, signal processing circuitry comprising: a. parity checking means having applied thereto the received signal and providing an output signal indicative of an error in the portion of the received signal associated with each of the parity bits checked; b. noise indication means having applied thereto the received signal for comparing the amplitude of each bit in the received signal to predetermined high and low levels and providing output signals indicating bits not exceeding said levels; c. separating means having applied thereto the received signal and separating the first and second messages therein; d. matching means connected to said separating means and matching each word in the first message to each word in the second message, said matching means providing an output signal indicative of matching words; and e. gating means connected to receive the output signals from said parity checking means, said noise indication means and said matching means, said gating means including circuitry for passing digital words in one of said first and second messages which do not have parity errors and which contain bits that exceed the high and low levels of the noise indication means, said gating means further including circuitry for passing digital words in one of said first and second messages which do not have parity errors, which contain bits that do not exceed the high and low levels of the noise indication means and which match, and said Gating means further including circuitry providing a flag signal when the same digital word in both the first and second messages contains one of a parity error, a parity error and bits which do not exceed the levels in the noise indication means, and a mismatch and bits which do not exceed the levels in the noise indication means.

Claim 19

In a communications system a receiver for receiving a signal composed of a first digital message interleaved with a second digital message, which is the first digital message repeated, and parity bits, signal processing circuitry as claimed in claim 15 including in addition display means connected to receive the digital words passed by said gating means and providing a visual display of characters representative of the digital words, said display means providing a visual display of a special character in response to a flag signal from said gating means.