Patent US3906386A successfully refreshed from Google Patents.
US3906386A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Transistor amplifier circuits with stabilized low current biasing
Assignee: Sony Corp
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Filing: 1973-05-23
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Granted: 1975-09-16
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Expires: 1993-05-23
Abstract
Abstract A transistor amplifying circuit having an amplifying transistor, a biasing transistor and an emitter follower transistor. The emitter follower is interposed between the signal source and the amplifying transistor to increase the input impedance of the circuit. Temperature compensating means are provided, and in one embodiment, a current sink is provided to increase the efficiency of supplying an input signal to the amplifying transistor.
Inventors
- 👤 Masayuki Hongu
- 👤 Isamu Ikeda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 18:02
CPC Classifications
H; H03; H03F; H03F1/00; H03F1/56; H03F1/30; H03F1/302
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
138 words
A transistor amplifier circuit comprising: a first transistor; a second transistor connected for supplying current bias to the first transistor; the second transistor having its collector direct current connected to its base through a first resistor; a third transiStor connected in the emitter follower configuration; a second resistor direct current connected between the collector of the second transistor and the base of said third transistor; said third transistor being coupled between said second resistor and said first transistor, the ratio of the first resistor to the second resistor being greater than one, the emitters of the first and second transistors being provided with third and fourth resistors, respectively, the ratio of the third resistor to the fourth resistor being greater than one, and a P-N junction device connected in series with the base-emitter path of said second transistor.
Claim 2
Dependent Claim
138 words
A transistor amplifier circuit comprising: a first transistor; a second transistor connected for supplying current bias to the first transistor; the second transistor having its collector direct current connected to its base through a first resistor; a third transiStor connected in the emitter follower configuration; a second resistor direct current connected between the collector of the second transistor and the base of said third transistor; said third transistor being coupled between said second resistor and said first transistor, the ratio of the first resistor to the second resistor being greater than one, the emitters of the first and second transistors being provided with third and fourth resistors, respectively, the ratio of the third resistor to the fourth resistor being greater than one, and a P-N junction device connected in series with the base-emitter path of said second transistor.
Claim 3
Dependent Claim
26 words
A transistor amplifier circuit in accordance with claim 1, wherein said P-N junction comprises a diode coupled in series with the emitter of said second transistor.
Claim 4
Dependent Claim
51 words
A transistor amplifier circuit in accordance with claim 1, wherein said P-N junction comprises a fourth transistor having its output connected in parallel with the output of the second transistor, its base coupled to the collector of the second transistor, and its emitter coupled to the base of the second transistor.
Claim 5
Dependent Claim
79 words
A transistor amplifier circuit in accordance with claim 2, further comprising a fourth transistor having its output terminals coupled in series with the output of said third transistor and its base coupled to a point between said diode and the emitter of said second transistor, whereby said fourth transistor acts as a constant current sink for said third transistor to improve the efficiency of supplying the input signal through said third transistor to the input of said first transistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-09-15 | 1979-03-17 | 1979-09-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-09-15 | 1983-03-17 | 1983-09-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-09-15 | 1987-03-17 | 1987-09-16 | $7700.00 | Window Closed / Lapsed |