Digital phase measuring system

Claim 3

first and second impedance transforming transistors fed by respectively the input signal and the inverting transistor,

Claim 4

first and second impedance transforming transistors fed by respectively the input signal and the inverting transistor,

Claim 5

A phase measuring system according to claim 1 wherein the discriminator comprises: a. a first NAND gate fed by the first output state of the first Schmitt trigger channel and the second output state of the second Schmitt trigger channel, the output being a first phase signal; b. a first inverting amplifier fed by the first NAND gate, the output being a second phase signal and complementary to the first phase signal; c. a second inverting amplifier fed by the second output of the first Schmitt trigger channel; d. a second NAND gate fed by the first and second inverting amplifiers; e. a third inverting amplifier fed by the first output state of the second Schmitt trigger channel; f. a third NAND gate fed by the first and third inverting amplifiers; and g. a second flip-flop fed by the second and third NAND gate and having an output indicating phase shift direction.

Claim 6

A phase measuring system according to claim 2 wherein the counting oscillator of the logic means is a square wave generator and said logic means further includes: a. a fourth NAND gate fed by the square wave generator and the first output of the first Schmitt trigger channel; b. a fifth NAND gate fed by the fourth NAND gate; c. a first means for counting a predetermined number of pulses including a sequence of frequency divider stages, the first counting means being fed by the fifth NAND gate; d. a first monostable multivibrator fed by the first counting means and generating a second input to the fifth NAND gate; e. a second monostable multivibrator fed by the first monostable multivibrator; f. a sixth NAND gate fed by the fifth NAND gate and the first inverting amplifier from the discriminator; g. a second means for counting a predetermined number of pulses including a sequence of frequency divider stages fed by the sixth NAND gate; h. a third flip-flop fed by the second counting means and the second monostable multivibrator; i. a first bistable latch circuit fed by the second flip-flop from the discriminator, the third flip-flop, and the first monostable multivibrator; j. second and third bistable latch circuits fed by one each of the last two of the sequence of frequency divider stages of the second counting means and by the first monostable multivibrator; k. first and second decoder means for converting binary coded decimals to 7-segment indications; and l. means for displaying the outputs of the first bistable latch circuit and the first and second decoding means.

Claim 7

first and second Schmitt trigger operational amplifiers fed respectively by the first and second impedance transforming transistors, and

Claim 8

first and second Schmitt trigger operational amplifiers fed respectively by the first and second impedance transforming transistors, and

Claim 9

a first flip-flop fed by the first and second operational amplifiers and having first and second complementary output states; b. a discriminator fed by the square wave outputs of the first and second Schmitt triggers for determining the coincidence thereof and producing a signal proportional to the phase difference of the two input signals; c. logic means including a counting oscillator for converting the length of the phase proportional signal from the discriminator to a digital signal; and d. a display fed by the logic means.

Claim 10

a first flip-flop fed by the first and second operational amplifiers and having first and second complementary output states; b. a discriminator fed by the square wave outputs of the first and second Schmitt triggers for determining the coincidence thereof and producing a signal proportional to the phase difference of the two input signals; c. logic means including a counting oscillator for converting the length of the phase proportional signal from the discriminator to a digital signal; and d. a display fed by the logic means.