Patent US3906256A successfully refreshed from Google Patents.
US3906256A
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Drive pulse generator for use in electronic analog display clock apparatus
Assignee: Toshiba Corp
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Filing: 1974-11-14
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Granted: 1975-09-16
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Expires: 1994-11-14
Abstract
Abstract Disclosed is a circuit for generating in a pulse motor drive coil an initial pulse motor drive pulse in a unit length of time during which a second hand is driven by one step, after resetting for time correction has been released. The output of a divider chain for frequency-dividing a standard frequency signal from a quartz oscillator into a signal having a period equal to the unit length of time is delayed by a delay circuit, and by a logic gate responsive to the output of the delay circuit and the output of the divider chain there is produced an output pulse signal having a period equal to the unit length of time and a narrower width. The output of the logic gate is supplied to a binary counter. An output circuitry responsive to the output of the binary counter and the output of the logic gate generates drive pulses in the drive coil. The reset signal is applied to the delay circuit and at least a frequency divider stage producing the signal the period of which equals the unit length of time.
Inventors
- 👤 Yasoji Suzuki
- 👤 Hisaharu Ogawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 06:12
CPC Classifications
G; G04; G04G; G04G3/00; G04G3/02; G04C; G04C3/00; G04C3/14; G04G5/00; G04G5/02
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
238 words
A drive pulse generator for use in an electronic analog display clock apparatus which is adapted to supply drive pulses to the drive coil of motor means for driving time indication hands, comprising: a standard frequency signal source; a frequency divider chain having binary counters cascadeconnected in a number of n-1 and connected to receive the output of said signal source for frequency-dividing said standard frequency signal in turn; a delay circuit connected to receive the output of the n-1 th stage binary counter of said frequency divider chain for delaying the output of said n-1 th stage binary counter in response to the output of one binary counter in said divider chain which produces a higher frequency signal than the output frequency of said n-1 th stage binary counter; logic gate means connected to receive the output of said delay circuit and an output of said n-1 th stage binary counter for producing an output pulse signal having a predetermined period and pulse width; a binary counter (nth stage) connected to receive the output of said logic gate; logic circuit means connected to receive output of said nth binary counter and output of said logic gate for producing in said drive coIl drive pulses passing therethrough at an interval of the predetermined period in mutually opposite directions; and resetting means for supplying a reset signal to at least said n1 stage binary counter and said delay circuit.
Claim 2
Dependent Claim
238 words
A drive pulse generator for use in an electronic analog display clock apparatus which is adapted to supply drive pulses to the drive coil of motor means for driving time indication hands, comprising: a standard frequency signal source; a frequency divider chain having binary counters cascadeconnected in a number of n-1 and connected to receive the output of said signal source for frequency-dividing said standard frequency signal in turn; a delay circuit connected to receive the output of the n-1 th stage binary counter of said frequency divider chain for delaying the output of said n-1 th stage binary counter in response to the output of one binary counter in said divider chain which produces a higher frequency signal than the output frequency of said n-1 th stage binary counter; logic gate means connected to receive the output of said delay circuit and an output of said n-1 th stage binary counter for producing an output pulse signal having a predetermined period and pulse width; a binary counter (nth stage) connected to receive the output of said logic gate; logic circuit means connected to receive output of said nth binary counter and output of said logic gate for producing in said drive coIl drive pulses passing therethrough at an interval of the predetermined period in mutually opposite directions; and resetting means for supplying a reset signal to at least said n1 stage binary counter and said delay circuit.
Claim 3
Dependent Claim
86 words
A drive pulse generator according to claim 1 wherein said logic circuit means includes first and second two-input logic gates, one side-inputs of said first and second two-input logic gates being coupled to an output of said logic gate means and the other side-inputs to the complementary outputs of said nth binary counter, and first and second inverters respectively connected to receive the outputs of said first and second two-input logic gates, said drive coil being connected between the outputs of said first and second inverters.
Claim 4
Dependent Claim
44 words
A drive pulse generator according to claim 1 wherein said resetting means includes means for stopping, when the output of said logic gate means is at a predetermined level, supply of the reset signal in response to said output of said logic gate means.
References Cited (Backward Citations)
US3765163A
Cited
US3852951A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-09-15 | 1979-03-17 | 1979-09-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-09-15 | 1983-03-17 | 1983-09-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-09-15 | 1987-03-17 | 1987-09-16 | $7700.00 | Window Closed / Lapsed |