Three-word adder carry propagation

Claim 2

An adder stage comprising means for receiving a first group of at least three summand bits, means for receiving a plurality of carry-in bits, carry output means, and means responsive to said summand bits and said carry-in bits for providing an plurality of carry-out bits to said carry output means, said carry-out bit providing means characterized by means for routing at least a selected one of said carry-in bits to said carry output means in accordance with a scheme allocating equal weights to said carry-out bits and in response to predetermined combinations of values of said summand bits.

Claim 3

The adder stage of claim 1 further comprising means operative in response to predetermined combinations of said summand bit values for generating at least a first one of said carry-out bits independently of said carry-in bits.

Claim 4

The adder stage of claim 2 wherein said carry-in bit receiving means includes first and second carry-in terminals and said carry output means includes first and second carry-out terminals, and wherein said routing means includes means for determining the total weight of said summand bits and means operative in response to each of a plurality of values of said total weight for establishing an associated carry-line path between a predetermined one of said carry-in terminals and a predetermined one of said carry-out terminals.

Claim 5

The adder stage of claim 3 wherein said carry-line path establishing means includes means operative when said total summand bit weight has first, second, third and fourth values for establishing a carry-line path between said second carry-in and first carry-out terminals, between said first carry-in and first carry-out terminals, between said second carry-in and second carry-out terminals and between said first carry-in and second carry-out terminals, respectively, said first, second, third and fourth values being of increasing magnitude in the order named.

Claim 6

The adder stage of claim 4 wherein said carry-out bit generating means includes means operative when said total summand bit weight has said second and said third values for providing said first one of said carry-out bits at said first carry-out terminal.

Claim 7

The adder stage of claim 4 further comprising means for receiving a second group of at least three summand bits, the bits of said second group having twice the weight of the bits of said first group.

Claim 8

The adder stage of claim 6 wherein said carry-out bit generating means includes means operative when the value of said total summand weight is greater than said second value for providing said first one of said carry-out bits at said first carry-out terminal and means operative when the value of said total summand weight is greater than said fourth value for providing a second one of said carry-out bits at said second carry-out terminal.

Claim 9

An adder stage comprising means for receiving three summand bit signals, first and second carry input means for receiving first and second carry-in bit sigNals, each of said summand bit signals and each of said carry-in bit signals being at one of two predetermined values, means for generating first and second carry-out bit signals, and first and second carry output means for receiving said first and second carry-out bit signals, respectively, said generating means characterized by means operative when none, one, two and three of said summand bit signals are at a selected one of said two predetermined values for establishing a conducting path between said second carry input means and said first carry output means, between said first carry input means and said first carry output means, between said second carry input means and said second carry output means, and between said first carry input means and said second carry output means, respectively.

Claim 10

An adder stage comprising means for receiving three summand bit signals, first and second carry input means for receiving first and second carry-in bit sigNals, each of said summand bit signals and each of said carry-in bit signals being at one of two predetermined values, means for generating first and second carry-out bit signals, and first and second carry output means for receiving said first and second carry-out bit signals, respectively, said generating means characterized by means operative when none, one, two and three of said summand bit signals are at a selected one of said two predetermined values for establishing a conducting path between said second carry input means and said first carry output means, between said first carry input means and said first carry output means, between said second carry input means and said second carry output means, and between said first carry input means and said second carry output means, respectively.

Claim 11

The adder stage of claim 8 further comprising means for applying a signal at said selected one of said values to said first carry output means when at least two of said summand bit signals are at said selected one of said values.

Claim 12

The adder stage of claim 9 further comprising means for generating a sum bit signal at said selected one of said values when a total odd number of said summand and carry-in bit signals are at said selected one of said values.

Claim 13

An adder stage comprising means for receiving a first group of three summand bit signals each having single weight, a second group of three summand bit signals each having double weight, first and second carry input means for receiving first and second carry-in bit signals, each of said summand bit signals and each of said carry-in bit signals being at either a first or a second predetermined value, means for generating first and second carry-out bit signals, and first and second carry output means for receiving said first and second carry-out bit signals, respectively, said generating means characterized by means operative when ones of said summand bits at said first predetermined value have a total weight of two, three, six and seven for establishing a conducting path between said second carry input means and said first carry output means, between said first carry input means and said first carry output means, between said second carry input means and said second carry output means, and between said first carry input means and said second carry output means, respectively.

Claim 14

An adder stage comprising means for receiving a first group of three summand bit signals each having single weight, a second group of three summand bit signals each having double weight, first and second carry input means for receiving first and second carry-in bit signals, each of said summand bit signals and each of said carry-in bit signals being at either a first or a second predetermined value, means for generating first and second carry-out bit signals, and first and second carry output means for receiving said first and second carry-out bit signals, respectively, said generating means characterized by means operative when ones of said summand bits at said first predetermined value have a total weight of two, three, six and seven for establishing a conducting path between said second carry input means and said first carry output means, between said first carry input means and said first carry output means, between said second carry input means and said second carry output means, and between said first carry input means and said second carry output means, respectively.

Claim 15

The adder stage of claim 11 further comprising means for applying a signal at said first predetermined value to said first carry output means when said total weight is at least four and means for applying a signal at said first predetermined value to said second carry output means when said total weight is at least eight.

Claim 16

The adder stage of claim 12 further comprising means for generating a first sum bit signal at said first predetermined value when a total odd number of said first group summand bit signals and said carry-out bit signals are at said first predetermined value and means for generating a second sum bit signal at said first predetermined value in accordance with the exclusive-OR function of first and second predetermined logic functions, said first logic function having a predetermined logic level if and only if two or three of said first group summand bit signals and said carry-in bit signals are at said first predetermined value and said second logic function having said predetermined logic level if and only if one or three of said second group summand bit signals are at said first predetermined value.

Claim 17

A three-word adder comprising; an ordered plurality of interconnected adder stages, each including means for receiving a first group of summand bits, first and second carry input means for receiving first and second carry-in bits, means for generating a first sum bit in response to said summand bits and said carry-in bits, first and second carry output means for providing first and second carry-out bits, and means responsive to said summand bits for routing at least a selected one of said carry-in bits to a selecTed one of said carry output means to generate at least one of said carry-out bits; and means for interconnecting said first and second carry output means of each of said stages to said first and second carry input means, respectively, of the next higher order stage in said adder.

Claim 18

A three-word adder comprising; an ordered plurality of interconnected adder stages, each including means for receiving a first group of summand bits, first and second carry input means for receiving first and second carry-in bits, means for generating a first sum bit in response to said summand bits and said carry-in bits, first and second carry output means for providing first and second carry-out bits, and means responsive to said summand bits for routing at least a selected one of said carry-in bits to a selecTed one of said carry output means to generate at least one of said carry-out bits; and means for interconnecting said first and second carry output means of each of said stages to said first and second carry input means, respectively, of the next higher order stage in said adder.

Claim 19

The three-word adder of claim 14 wherein each of said summand bits has either a 0 or 1 value and wherein said routing means includes means operative when one and three of said summand bits have the value 1 for routing said first carry-in bit to said first and second carry output means, respectively, and means operative when none and two of said summand bits have the value 1 for routing said second carry-in bit to said first and second carry output means, respectively.

Claim 20

The three-word adder of claim 15 further including means operative when at least two of said summand bits have the value 1 for providing said first carry-out bit with the value 1.

Claim 21

A three-word adder comprising, an ordered plurality of interconnected adder stages each including means for receiving a first group of summand bits which each have a first weight, means for receiving a second group of three summand bits which each have a second weight, said second weight being twice said first weight, each of said first group and second group summand bits having either a 0 or 1 value, first and second carry input means for receiving first and second carry-in bits, means for generating first and second sum bits in response to said first and second summand bit groups and said carry-in bits, first and second carry output means for providing first and second carry-out bits, means operative when the total weight of said summand bits having the value 1 is three and seven for routing said first carry-in bit to said first and second carry output means, respectively, and means operative when said total weight is two and six for routing said second carry-in bit to said first and second carry output means, respectively, and means for connecting said first and second carry output means of each of said stages to said first and second carry input means, respectively, of the next higher order stage in said adder.

Claim 22

A three-word adder comprising, an ordered plurality of interconnected adder stages each including means for receiving a first group of summand bits which each have a first weight, means for receiving a second group of three summand bits which each have a second weight, said second weight being twice said first weight, each of said first group and second group summand bits having either a 0 or 1 value, first and second carry input means for receiving first and second carry-in bits, means for generating first and second sum bits in response to said first and second summand bit groups and said carry-in bits, first and second carry output means for providing first and second carry-out bits, means operative when the total weight of said summand bits having the value 1 is three and seven for routing said first carry-in bit to said first and second carry output means, respectively, and means operative when said total weight is two and six for routing said second carry-in bit to said first and second carry output means, respectively, and means for connecting said first and second carry output means of each of said stages to said first and second carry input means, respectively, of the next higher order stage in said adder.

Claim 23

The three-word adder of claim 17 wherein each of said stages further includes means operative when said total weight is at least four for providing said first carry-out bit with the value 1 and means operative when said total weight is at least eight for providing said second carry-out bit with the value 1.

Claim 24

In a three-word adder stage adapted for receiving a plurality of summand bits and two carry-in bits, a method for providing a sum bit and for providing first and second carry-out bits at respective associated first and second carry output terminals, said method comprising the steps of generating said sum bit in response to said summand and said carry-in bits, determining the total weight of said summand bits, generating a selected one of said carry-out bits on the basis of said total weight and providing said selected carry-out bit at the associated one of said carry-out terminals, said selected carry-out bit having a weight twice that of said sum bit, and selecting one of said carry-in bits on the basis of said total weight and routing said selected carry-in bit to the other of said carry output terminals to provide the other of said carry-out bits, said other carry-out bit having a weight twice that of said sum bit.

Claim 25

In a three-word adder stage adapted for receiving a plurality of summand bits and two carry-in bits, a method for providing a sum bit and for providing first and second carry-out bits at respective associated first and second carry output terminals, said method comprising the steps of generating said sum bit in response to said summand and said carry-in bits, determining the total weight of said summand bits, generating a selected one of said carry-out bits on the basis of said total weight and providing said selected carry-out bit at the associated one of said carry-out terminals, said selected carry-out bit having a weight twice that of said sum bit, and selecting one of said carry-in bits on the basis of said total weight and routing said selected carry-in bit to the other of said carry output terminals to provide the other of said carry-out bits, said other carry-out bit having a weight twice that of said sum bit.

Claim 26

The method of claim 19 wherein said selecting and routing step includes the steps of routing said first carry-in bit to said first and second carry output terminals when said total weight has second and fourth values, respectively, and routing said second carry-in bit to said first and second carry output terminals when said total weight has first and third values, respectively, said first, second, third and fourth values being of increasing magnitude in the order named.

Claim 27

The method of clAim 20 wherein said carry-out bit generating and providing step includes the steps of generating said second carry-out bit when total weight has said first and second values and generating said first carry-out bit when said total weight has said third and fourth values.

Claim 28

The method of claim 20 wherein said carry-out bit generating and providing step includes the steps of providing said first carry-out bit with a first predetermined value when the magnitude of said total weight is greater than said second value and providing said second carry-out bit with a second predetermined value when the magnitude of said total weight is less than said third value and with said first predetermined value when said total weight is greater than said fourth value.