Patent US3906199A successfully refreshed from Google Patents.
US3906199A
Expired / Lapsed
US
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Digital filter circuit
Assignee: AT&T Inc
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Filing: 1974-12-13
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Granted: 1975-09-16
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Expires: 1994-12-13
Abstract
Abstract Apparatus in a digital filter circuit for substantially eliminating limit cycle noise comprises means for randomly inhibiting the rounding signal in at least one of the multipliers comprising the digital filter circuit.
Inventors
- 👤 Robert Bruce Kieburtz
- 👤 Kent Vincent Mina
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 18:03
CPC Classifications
H; H03; H03H; H03H17/00; H03H17/02; H03H17/04; H03H17/0461
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
182 words
Apparatus in a digital filter for generating the product of an ordered N-bit binary data word and an M-bit multiplier word, M > OR = 2, comprising A. M substantially identical stages, each comprising 1. means for forming the bitwise product of one bit of said multiplier word and each bit of said data word, 2. means for forming successive partial sums of said bitwise products and partial products of equal significance generated at a preceding stage, and 3. means for periodically blanking the one of said partial sums having lowest significance, B. means for applying input partial sums generated at stage i to stage i+1 for i 1,2, . . . M-1, said input partial sum applied at stage 1 being uniformly 0, and C. means for applying a logic 1 signal to said first stage of said multiplier at an interval such that it is ANDed with the partial product term having highest significance which is blanked by said means for periodically blanking, and D. means for controllably suppressing the generation of logic 1 signals by said means for applying.
Claim 2
Dependent Claim
182 words
Apparatus in a digital filter for generating the product of an ordered N-bit binary data word and an M-bit multiplier word, M > OR = 2, comprising A. M substantially identical stages, each comprising 1. means for forming the bitwise product of one bit of said multiplier word and each bit of said data word, 2. means for forming successive partial sums of said bitwise products and partial products of equal significance generated at a preceding stage, and 3. means for periodically blanking the one of said partial sums having lowest significance, B. means for applying input partial sums generated at stage i to stage i+1 for i 1,2, . . . M-1, said input partial sum applied at stage 1 being uniformly 0, and C. means for applying a logic 1 signal to said first stage of said multiplier at an interval such that it is ANDed with the partial product term having highest significance which is blanked by said means for periodically blanking, and D. means for controllably suppressing the generation of logic 1 signals by said means for applying.
Claim 3
Dependent Claim
22 words
means for forming successive partial sums of said bitwise products and partial products of equal significance generated at a preceding stage, and
Claim 4
Dependent Claim
22 words
means for forming successive partial sums of said bitwise products and partial products of equal significance generated at a preceding stage, and
Claim 5
Dependent Claim
42 words
Apparatus as in claim 1 wherein said means for controllably suppressing the generation of logic 1 signals comprises means for randomly generating logic 0 signals and an AND gate for ANDing said logic 1 signals and said randomly generated logic 0 signals.
Claim 6
Dependent Claim
103 words
means for periodically blanking the one of said partial sums having lowest significance, B. means for applying input partial sums generated at stage i to stage i+1 for i 1,2, . . . M-1, said input partial sum applied at stage 1 being uniformly 0, and C. means for applying a logic 1 signal to said first stage of said multiplier at an interval such that it is ANDed with the partial product term having highest significance which is blanked by said means for periodically blanking, and D. means for controllably suppressing the generation of logic 1 signals by said means for applying.
Claim 7
Dependent Claim
103 words
means for periodically blanking the one of said partial sums having lowest significance, B. means for applying input partial sums generated at stage i to stage i+1 for i 1,2, . . . M-1, said input partial sum applied at stage 1 being uniformly 0, and C. means for applying a logic 1 signal to said first stage of said multiplier at an interval such that it is ANDed with the partial product term having highest significance which is blanked by said means for periodically blanking, and D. means for controllably suppressing the generation of logic 1 signals by said means for applying.
Claim 8
Dependent Claim
28 words
Apparatus as in claim 2 wherein said means for randomly generating logic 0 signals comprises a random noise generator and a D flip-flop responsive to said noise generator.
Claim 9
Dependent Claim
40 words
Apparatus as in claim 1 wherein said means for controllably suppressing the generation of logic 1 signals comprises means for generating logic 0 signals and for controlling the probability of the occurrence of a logic 0 during a given interval.
References Cited (Backward Citations)
US3609568A
Cited
US3749895A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-09-15 | 1979-03-17 | 1979-09-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-09-15 | 1983-03-17 | 1983-09-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-09-15 | 1987-03-17 | 1987-09-16 | $7700.00 | Window Closed / Lapsed |