Surface charge transistor devices

Claim 2

A SEMICONDUCTOR DEVICE COMPRISING A SUBSTRATE OF SEMICONDUCTOR MATERIAL OF ONE CONDUCTIVITY TYPE, A FIRST SOURCE CONDUCTOR MEMBER INSULATING OVERLYING SAID SUBSTRATE, A FIRST, RECIEVER CONDUCTOR MEMBER INSULATING OVERLYING SAID SUBSTRATE, A FIRST TRANSFER GATE CONDUCTOR MEMBER INSULATING OVERLYING SAID SUBSTRATE AND HAVING AT LEAST A PORTION THEREOF SPACED BETWEEN SAID FIRST SOURCE CONDUCTOR MEMBER AND SAID FIRST RECEIVER CONDUCTOR MEMBER AND INSULATED FROM SAID FIRST SOURCE CONDUCTOR MEMBER AND SAID FIRST RECEIVER CONDUCTOR MEMBER, MEANS APPLYING A FIRST VOLTAGE BETWEEN SAID FIRST SOURCE CONDUCTOR MEMBER AND SAID SUBSTRATE TO FORM A FIRST CHARGE STORAGE REGION IN SAID SUBSTRATE, MEANS APPLYING SECOND VOLTAGE BETWEEN SAID FIRST RECEIVER CONDUCTOR MEMBER AND SAID SUBSTRATE TO FORM A SECOND CHARGE STORAGE REGION IN SAID SUBSTRATE, SAID SECOND CHARGE STORAGE REGON BEING SPACED FROM SAID FIRST CHARGE

Claim 3

The semiconductor device of claim 1 in which said first transfer gate conductor member insulatingly overlies and at least partially overlaps portions of said first source conductor member and said first receiver conductor member.

Claim 4

The combination of claim 1 including means for introducing charge into said first storage region and means for removing charge from said second storage region.

Claim 5

The device of claim 1 in which is included a second receiver conductor member insulatingly overlying said substrate, a second transfer gate conductor member insulatingly overlying said substrate and having at least a portion thereof spaced between said first source conductor member and said second receiver conductor member, means applying said second voltage between said second receiver conductor member and said substrate to form a third charge storage region in said substrate, said third charge storage region being spaced from said first charge storage region to form a second barrier region therebetween and underlying said second transfer gate conductor member, means applying a fourth voltage between said second transfer gate conductor member and said substrate for controllably varying the surface potential of said second barrier region for controlling the transfer of charge from said first storage region to said third storage region.

Claim 6

A semiconductor device comprising a substrate of semiconductor material of one conductivity type, a first source conductor member insulatingly overlying said substrate, a first receiver conductor member insulatingly overlying said substrate, a first transfer gate conductor member insulatingly overlying said substrate and having at least a portion thereof spaced between said first source conductor member and said first receiver conductor member and insulated from said first source conductor member and said first receiver conductor member, means applying a first voltage between said first source conductor member and said substrate to form a first charge storage region in said substrate, means applying a second voltage between said first receiver conductor member and said substrate to form a second charge storage region in said substrate, said second charge storage regiOn being spaced from said first charge storage region to form a barrier region between said storage regions and underlying said first transfer gate conductor member, means applying a third voltage between said first transfer gate conductor member and said substrate for controllably varying the surface potential of said barrier region for controlling the transfer of charge from said first storage region to said second storage region, the charge storage capacity of said first storage region being greater than the charge storage capacity of said second storage region.

Claim 7

A semiconductor device comprising a substrate of semiconductor material of one conductivity type, a first source conductor member insulatingly overlying said substrate, a first receiver conductor member insulatingly overlying said substrate, a first transfer gate conductor member insulatingly overlying said substrate and having at least a portion thereof spaced between said first source conductor member and said first receiver conductor member and insulated from said first source conductor member and said first receiver conductor member, means applying a first voltage between said first source conductor member and said substrate to form a first charge storage region in said substrate, means applying a second voltage between said first receiver conductor member and said substrate to form a second charge storage region in said substrate, said second charge storage regiOn being spaced from said first charge storage region to form a barrier region between said storage regions and underlying said first transfer gate conductor member, means applying a third voltage between said first transfer gate conductor member and said substrate for controllably varying the surface potential of said barrier region for controlling the transfer of charge from said first storage region to said second storage region, the charge storage capacity of said first storage region being greater than the charge storage capacity of said second storage region.

Claim 8

The device of claim 5 in which the area of said first receiver conductor member is less than the area of said first source conductor member.

Claim 9

A semiconductor device comprising a substrate of semiconductor material of one conductivity type, a first source conductor member insulatingly overlying said substrate, a first receiver conductor member insulatingly overlying said substrate, a first transfer gate conductor member insulatingly overlying said substrate and having at least a portion thereof spaced between said first source conductor member and said first receiver conductor member and insulated from said first source conductor member and said first receiver conductor member, means applying a first voltage between said first source conductor member and said substrate to form a first charge storage region in said substrate, means applying a second voltage between said first receiver conductor member and said substrate to form a second charge storage region in said substrate, said second charge storage region being spaced from said first charge storage region to form a barrier region between said storage regions and underlying said first transfer gate conductor member, means applying a third voltage between said first transfer gate conductor member and said substrate for controllably varying the surface potential of said barrier region for controlling the transfer of charge from said first storage region to said second storage region, a second source conductor member insulatingly overlying said substrate, said first transfer gate conductor member insulatingly overlying said substrate having at least a portion thereof spaced between said second source conductor member and said first receiver conductor member, means applying said first voltage between said second source conductor member and said substrate to form a third charge storage region in said substrate, said third charge storage region being spaced from said second charge storage region to form a second barrier region underlying said first transfer gate conductor member, said third voltage controllably varying the surface potential of said second barrier region for controlling the transfer of charge from said third charge storage region to said second charge storage region.

Claim 10

A semiconductor device comprising a substrate of semiconductor material of one conductivity type, a first source conductor member insulatingly overlying said substrate, a first receiver conductor member insulatingly overlying said substrate, a first transfer gate conductor member insulatingly overlying said substrate and having at least a portion thereof spaced between said first source conductor member and said first receiver conductor member and insulated from said first source conductor member and said first receiver conductor member, means applying a first voltage between said first source conductor member and said substrate to form a first charge storage region in said substrate, means applying a second voltage between said first receiver conductor member and said substrate to form a second charge storage region in said substrate, said second charge storage region being spaced from said first charge storage region to form a barrier region between said storage regions and underlying said first transfer gate conductor member, means applying a third voltage between said first transfer gate conductor member and said substrate for controllably varying the surface potential of said barrier region for controlling the transfer of charge from said first storage region to said second storage region, a second source conductor member insulatingly overlying said substrate, said first transfer gate conductor member insulatingly overlying said substrate having at least a portion thereof spaced between said second source conductor member and said first receiver conductor member, means applying said first voltage between said second source conductor member and said substrate to form a third charge storage region in said substrate, said third charge storage region being spaced from said second charge storage region to form a second barrier region underlying said first transfer gate conductor member, said third voltage controllably varying the surface potential of said second barrier region for controlling the transfer of charge from said third charge storage region to said second charge storage region.

Claim 11

A semiconductor device comprising a substrate of semiconductor material of one conductivity type, a plurality of source and receiver conductor members insulatingly overlying said substrate, a plurality of transfer gate conductor members insulatingly overlying said substrate, each spaced between adjacent source and receiver conductor members, means applying a first pulsating voltage to alternate ones of said source and receiver conductor members to form first charge storage regions in said one conductivity substrate, means applying a second pulsating voltage oppositely phased with respect to said first pulsating voltage between the other of said source and receiver conductor members to form second charge storage regions in said one conductivity substrate, said second charge storage regions being spaced from said first charge storage regions to form a plurality of barrier regions within said one conductivity substrate each underlying a respective one of said transfer gate conductor members, means applying a third pulsating voltage different from said first and second pulsating voLtages to one set of alternate transfer gate conductor members for alternately lowering the potentials of a corresponding set of barrier regions to permit charge transfer thereacross, means applying a fourth pulsating voltage different from said first and second pulsating voltages to the other set of alternate transfer gate conductor members for alternately lowering the potentials of a corresponding set of barrier regions to permit charge transfer thereacross, said third and fourth voltages being oppositely phased with respect to one another and being synchronized with said first and second voltages.

Claim 12

A semiconductor device comprising a substrate of semiconductor material of one conductivity type, a plurality of source and receiver conductor members insulatingly overlying said substrate, a plurality of transfer gate conductor members insulatingly overlying said substrate, each spaced between adjacent source and receiver conductor members, means applying a first pulsating voltage to alternate ones of said source and receiver conductor members to form first charge storage regions in said one conductivity substrate, means applying a second pulsating voltage oppositely phased with respect to said first pulsating voltage between the other of said source and receiver conductor members to form second charge storage regions in said one conductivity substrate, said second charge storage regions being spaced from said first charge storage regions to form a plurality of barrier regions within said one conductivity substrate each underlying a respective one of said transfer gate conductor members, means applying a third pulsating voltage different from said first and second pulsating voLtages to one set of alternate transfer gate conductor members for alternately lowering the potentials of a corresponding set of barrier regions to permit charge transfer thereacross, means applying a fourth pulsating voltage different from said first and second pulsating voltages to the other set of alternate transfer gate conductor members for alternately lowering the potentials of a corresponding set of barrier regions to permit charge transfer thereacross, said third and fourth voltages being oppositely phased with respect to one another and being synchronized with said first and second voltages.

Claim 13

The semiconductor device of claim 8 including means for introducing electrical charge into one of said first storage regions, and means for removing electrical charge from one of said second storage regions.

Claim 14

The device of claim 8 in which the capacitance of each of said first transfer gate conductor members in relation to said substrate and in relation to a respective adjacent one of said first source conductor members and a respective adjacent one of said first receiver conductor members is less than the capacitance of said adjacent one of said first source conductor members.

Claim 15

The device of claim 8 in which the leading and lagging edges of each pulse of said third pulsating voltage lies between the leading and lagging edges of a respective pulse of said first pulsating voltage, and in which the leading and lagging edges of each pulse of said fourth pulsating voltage lying between the lagging edge of a respective pulse of said first pulsating voltage and the leading edge of a succeeding pulse of said first pulsating voltage.

Claim 16

A semiconductor device comprising a substrate of semiconductor material of one conductivity type, a first source conductor member insulatingly overlying said substrate, a first receiver conductor member insulatingly overlying said substrate, a first transfer gate conductor member insulatingly overlying said substrate and having at least a portion thereof spaced between said first source conductor member and said first receiver conductor member and insulated from said first source conductor member and said first receiver conductor member, means applying a first voltage between said first source conductor member and said substrate to form a first charge storage region in said substrate, means applying a second voltage between said first receiver conductor member and said substrate to form a second charge storage region in said substrate, said second charge storage region being spaced from said first charge storage region to form a barrier region between said storage regions and underlying said first transfer gate conductor member, means applying a third voltage between said first transfer gate conductor member and said substrate for controllably varying the surface potential of said barrier region for controlling the transfer of charge from said first storage region to said second storage region, the capacitance of said first storage region being greater than the capacitance of said first transfer gate conductor member in relation to said substrate and in relation to said first source conductor member and said first receiver conductor member whereby the charge required to be supplied to said first transfer gate conductor member to effect transfer of a given quantity of charge from said first storage region to said second storage region is less than said given quantity of charge.

Claim 17

A semiconductor device comprising a substrate of semiconductor material of one conductivity type, a first source conductor member insulatingly overlying said substrate, a first receiver conductor member insulatingly overlying said substrate, a first transfer gate conductor member insulatingly overlying said substrate and having at least a portion thereof spaced between said first source conductor member and said first receiver conductor member and insulated from said first source conductor member and said first receiver conductor member, means applying a first voltage between said first source conductor member and said substrate to form a first charge storage region in said substrate, means applying a second voltage between said first receiver conductor member and said substrate to form a second charge storage region in said substrate, said second charge storage region being spaced from said first charge storage region to form a barrier region between said storage regions and underlying said first transfer gate conductor member, means applying a third voltage between said first transfer gate conductor member and said substrate for controllably varying the surface potential of said barrier region for controlling the transfer of charge from said first storage region to said second storage region, the capacitance of said first storage region being greater than the capacitance of said first transfer gate conductor member in relation to said substrate and in relation to said first source conductor member and said first receiver conductor member whereby the charge required to be supplied to said first transfer gate conductor member to effect transfer of a given quantity of charge from said first storage region to said second storage region is less than said given quantity of charge.

Claim 18

A semiconductor device comprising a substrate of semiconductor material of one conductivity type, a first source conductor member insulatingly overlying said substrate, a first receiver conductor member insulatingly overlying said substrate, a first transfer gate conductor member insulatingly overlying said substrate and having at least a portion thereof spaced between said first source conductor member and said first receiver conductor member and insulated from said first source conductor member and said first receiver conductor member, means applying a first voltage between said first source conductor member and said substrate to form a first charge storage region in said substrate, means applying a second voltage between said first receiver conductor member and said substrate to form a second charge storage region in said substrate, said second charge storage region being spaced from said first charge storage region to form a barrier region between said storage regions and underlying said first transfer gate conductor member, means applying a third voltage between said first transfer gate conductor member and said substrate for controllably varying the surface potential of said barrier region for controlling the transfer of charge from said first storage region to said second storage region, a second transfer gate conductor member insulatingly overlying said substrate and having at least a portion thereof spaced between said first transfer gate conductor member and one of said source and receiver conductor members, said first transfer gate conductor member overlying one portion of said barrier region and said second transfer gate conductor member overlying another portion of said barrier region, said portions of said barrier region arranged in side by side relationship between said first storage region and said second storage region, means applying a fourth voltage between said second transfer gate conductor member and said substrate for controllably varying the surface potential of said other portion of said barrier region for controlling the transfer of charge from said first storage region to said second storage region.

Claim 19

A semiconductor device comprising a substrate of semiconductor material of one conductivity type, a first source conductor member insulatingly overlying said substrate, a first receiver conductor member insulatingly overlying said substrate, a first transfer gate conductor member insulatingly overlying said substrate and having at least a portion thereof spaced between said first source conductor member and said first receiver conductor member and insulated from said first source conductor member and said first receiver conductor member, means applying a first voltage between said first source conductor member and said substrate to form a first charge storage region in said substrate, means applying a second voltage between said first receiver conductor member and said substrate to form a second charge storage region in said substrate, said second charge storage region being spaced from said first charge storage region to form a barrier region between said storage regions and underlying said first transfer gate conductor member, means applying a third voltage between said first transfer gate conductor member and said substrate for controllably varying the surface potential of said barrier region for controlling the transfer of charge from said first storage region to said second storage region, a second transfer gate conductor member insulatingly overlying said substrate and having at least a portion thereof spaced between said first transfer gate conductor member and one of said source and receiver conductor members, said first transfer gate conductor member overlying one portion of said barrier region and said second transfer gate conductor member overlying another portion of said barrier region, said portions of said barrier region arranged in side by side relationship between said first storage region and said second storage region, means applying a fourth voltage between said second transfer gate conductor member and said substrate for controllably varying the surface potential of said other portion of said barrier region for controlling the transfer of charge from said first storage region to said second storage region.

Claim 20

A semiconductor device comprising a substrate of semiconductor material of one conductivity type, a first source conductor member insulatingly overlying said substrate, a first receiver conductor member insulatingly overlying said substrate, a first transfer gate conductor member insulatingly overlying said substrate and having at least a portion thereof spaced between said first source conductor member and said first receiver conductor member and insulated from said first source conductor member and said first receiver conductor member, means applying a first voltage between said first source conductor member and said substrate to form a first charge storage region in said substrate, means applying a second voltage between said first receiver conductor member and said substrate to form a second charge storage region in said substrate, said second charge storage region being spaced from said first charge storage region to form a barrier region between said storage regions and underlying said first transfer gate conductor member, means applying a third voltage between said first transfer gate conductor member and said substrate for controllably varying the surface potential of said barrier region for controlling the transfer of charge from said first storage region to said second storage region, a second transfer gate conductor member insulatingly overlying said substrate and having at least a portion thereof spaced between said first transfer gate conductor member and one of said source and receiver conductor members, said first transfer gate conductor member overlying one portion of said barrier region and said second transfer gate conductor member overlying another portion of said barrier region, said portions of said barrier region arranged in end-to-end relationship between said first storage region and said second storage region, means applying a fourth voltage between said second transfer gate conductor member and said substrate for controllably varying the surface potential of said other portion of said barrier region for controlling the transfer of charge from said first storage region to said second storage region.

Claim 21

A semiconductor device comprising a substrate of semiconductor material of one conductivity type, a first source conductor member insulatingly overlying said substrate, a first receiver conductor member insulatingly overlying said substrate, a first transfer gate conductor member insulatingly overlying said substrate and having at least a portion thereof spaced between said first source conductor member and said first receiver conductor member and insulated from said first source conductor member and said first receiver conductor member, means applying a first voltage between said first source conductor member and said substrate to form a first charge storage region in said substrate, means applying a second voltage between said first receiver conductor member and said substrate to form a second charge storage region in said substrate, said second charge storage region being spaced from said first charge storage region to form a barrier region between said storage regions and underlying said first transfer gate conductor member, means applying a third voltage between said first transfer gate conductor member and said substrate for controllably varying the surface potential of said barrier region for controlling the transfer of charge from said first storage region to said second storage region, a second transfer gate conductor member insulatingly overlying said substrate and having at least a portion thereof spaced between said first transfer gate conductor member and one of said source and receiver conductor members, said first transfer gate conductor member overlying one portion of said barrier region and said second transfer gate conductor member overlying another portion of said barrier region, said portions of said barrier region arranged in end-to-end relationship between said first storage region and said second storage region, means applying a fourth voltage between said second transfer gate conductor member and said substrate for controllably varying the surface potential of said other portion of said barrier region for controlling the transfer of charge from said first storage region to said second storage region.

Claim 22

A semiconductor device comprising a substrate of semiconductor material of one conductivity type, a plurality of Source and receiver conductor members insulatingly overlying said substrate, a plurality of transfer gate conductor members insulatingly overlying said substrate, each spaced between respective adjacent source and receiver conductor members, means applying a first pulsating voltage to alternate ones of said source and receiver conductor members to form first charge storage regions in said substrate, means applying a second pulsating voltage between the other of said source and receiver conductor members to form second charge storage regions in said substrate, said second charge storage regions being spaced from said first charge storage regions to form a plurality of barrier regions each underlying a respective one of said transfer gate conductor members, means applying third and fourth phase related pulsating voltages to said transfer gate electrodes to control the transfer of charge therein from said first storage regions to said second storage regions, said source and receiver conductor members and associated transfer gate members being arranged into a pair of input signal channels and an output signal channel, the terminal storage region of one input channel and the initial storage region of said output channel forming a first interchannel barrier region, the terminal storage region of the other input channel and the initial storage region of said output channel forming a second interchannel barrier region, an interchannel transfer gate conductor member included between the terminal source and receiver conductor members of said input channels and the initial source and receiver conductor member of said output channel and overlying said interchannel barrier regions, means applying a fifth voltage between said interchannel transfer gate conductor member and said substrate for controllably varying the surface potential of said interchannel barrier regions for controlling the transfer of charge from the terminal storage regions of said input channels to the initial storage region of said output channel.

Claim 23

A semiconductor device comprising a substrate of semiconductor material of one conductivity type, a plurality of Source and receiver conductor members insulatingly overlying said substrate, a plurality of transfer gate conductor members insulatingly overlying said substrate, each spaced between respective adjacent source and receiver conductor members, means applying a first pulsating voltage to alternate ones of said source and receiver conductor members to form first charge storage regions in said substrate, means applying a second pulsating voltage between the other of said source and receiver conductor members to form second charge storage regions in said substrate, said second charge storage regions being spaced from said first charge storage regions to form a plurality of barrier regions each underlying a respective one of said transfer gate conductor members, means applying third and fourth phase related pulsating voltages to said transfer gate electrodes to control the transfer of charge therein from said first storage regions to said second storage regions, said source and receiver conductor members and associated transfer gate members being arranged into a pair of input signal channels and an output signal channel, the terminal storage region of one input channel and the initial storage region of said output channel forming a first interchannel barrier region, the terminal storage region of the other input channel and the initial storage region of said output channel forming a second interchannel barrier region, an interchannel transfer gate conductor member included between the terminal source and receiver conductor members of said input channels and the initial source and receiver conductor member of said output channel and overlying said interchannel barrier regions, means applying a fifth voltage between said interchannel transfer gate conductor member and said substrate for controllably varying the surface potential of said interchannel barrier regions for controlling the transfer of charge from the terminal storage regions of said input channels to the initial storage region of said output channel.

Claim 24

A semiconductor device comprising a substrate of semiconductor material of one conductivity type, a plurality of source and receiver conductor members insulatingly overlying said substrate, a plurality of transfer gate conductor members insulatingly overlying said substrate, each spaced between respective adjacent source and receiver conductor members, means applying a first pulsating voltage to alternate ones of said source and receiver conductor members to form first charge storage regions in said substrate, means for applying a second pulsating voltage between the other of said source and receiver conductor members to form second charge storage regions in said substrate, said second charge storage regions being spaced from said first charge storage regions to form a plurality of barrier regions each underlying a respective one of said transfer gate conductor members, means applying third and fourth phase related pulsating voltages to said transfer gate electrodes to control the transfer of charge therein from said first storage regions to said second storage regions, said third and fourth phase related pulsating voltages being different from either of said first and second pulsating voltages, said third and fourth voltages being oppositely phased with respect to one another and being synchronized with said first and second voltages, said source and receiver conductor members and associated transfer gate members being arranged into an input signal channel and a pair of output signal channels, the terminal storage region of the input channel and the initial storage region of one of said output channels forming a first interchannel barrier region, the terminal storage region of the input channel and the initial storage region of the other of said output channels forming a second interchannel barrier region, a first interchannel transfer gate conductor member included between the terminal source and receiver conductor member of said input channel and the initial source and receiver conductor member of one of said output channels and overlying said first interchannel barrier region, a second interchannel transfer gate conductor member included between the terminal source and receiver conductor member of said input channel and the initial source and receiver conductor member of the other of said output channels and overlying said second interchannel barrier region, means applying a first control voltage between said first interchannel transfer gate conductor member and said substrate for controllably varying the surface potential of said first interchannel barrier region for controlling the transfer of charge from the terminal storage region of said input channel to the initial storage region of said one output channel, means applying a second control voltage between said second interchannel transfer gate conductor member and said substrate for controllably varying the surface potential of said second interchannel barrier region for controlling the transfer of charge from the terminal storage region of said input channel to the initial storage region of said other output channel.

Claim 25

A semiconductor device comprising a substrate of semiconductor material of one conductivity type, a plurality of source and receiver conductor members insulatingly overlying said substrate, a plurality of transfer gate conductor members insulatingly overlying said substrate, each spaced between respective adjacent source and receiver conductor members, means applying a first pulsating voltage to alternate ones of said source and receiver conductor members to form first charge storage regions in said substrate, means for applying a second pulsating voltage between the other of said source and receiver conductor members to form second charge storage regions in said substrate, said second charge storage regions being spaced from said first charge storage regions to form a plurality of barrier regions each underlying a respective one of said transfer gate conductor members, means applying third and fourth phase related pulsating voltages to said transfer gate electrodes to control the transfer of charge therein from said first storage regions to said second storage regions, said third and fourth phase related pulsating voltages being different from either of said first and second pulsating voltages, said third and fourth voltages being oppositely phased with respect to one another and being synchronized with said first and second voltages, said source and receiver conductor members and associated transfer gate members being arranged into an input signal channel and a pair of output signal channels, the terminal storage region of the input channel and the initial storage region of one of said output channels forming a first interchannel barrier region, the terminal storage region of the input channel and the initial storage region of the other of said output channels forming a second interchannel barrier region, a first interchannel transfer gate conductor member included between the terminal source and receiver conductor member of said input channel and the initial source and receiver conductor member of one of said output channels and overlying said first interchannel barrier region, a second interchannel transfer gate conductor member included between the terminal source and receiver conductor member of said input channel and the initial source and receiver conductor member of the other of said output channels and overlying said second interchannel barrier region, means applying a first control voltage between said first interchannel transfer gate conductor member and said substrate for controllably varying the surface potential of said first interchannel barrier region for controlling the transfer of charge from the terminal storage region of said input channel to the initial storage region of said one output channel, means applying a second control voltage between said second interchannel transfer gate conductor member and said substrate for controllably varying the surface potential of said second interchannel barrier region for controlling the transfer of charge from the terminal storage region of said input channel to the initial storage region of said other output channel.

Claim 26

A semiconductor device comprising a substrate of semiconductor material of one conductivity type, a plurality of source and receiver conductor members insulatingly overlying said substrate, a plurality of transfer gate conductor members insulatingly overlying said substrate, each spaced between adjacent source and receiver conductor members, said source and receiver conductor members being arranged in a plurality of rows and a plurality of columns, the conductor members in odd columns being conductively interconnected and the conductor members in even columns being conductively interconnected, said transfer gate conductor members being arranged in a plurality of rows and a plurality of columns, in each of the rows the conductor members located in odd columns being interconnected and the conductor members located in even columns being interconnected, means applying a fixed bias voltage to said source and receiver conductor members to establish storage regions in said substrate underlying said conductor members, means applying a first voltage of one phase to the source and receiver conductor members in the odd columns to form first charge storage regions in said substrate, means applying a second voltage of the opposite phase to the source and receiver conductor members in the even columns to form second charge storage regions in said one conductivity substrate, said second charge storage regions being spaced from said first charge storage regions to form a plurality of barrier regions within said one conductivity substrate each underlying a respective one of said transfer gate conductor members, means selectively applying a pair of oppositely phased control voltages to a row of said transfer gate conductor members, one of said control voltages being applied to the transfer gate conductor members in odd columns for alternately lowering the potentials of corresponding barrier regions to permit charge transfer thereacross and the other of said voltages being applied to the transfer gate conductor members in the even columns for alternately lowering the potentials of corresponding barrier regions to permit charge transfer thereacross, said pair of oppositely phased voltages being synchronized with said first and second voltages, whereby charge is selectively transferred in the charge storage regions in the row of source and receiver conductor members associated with said row of transfer gate conductor members, means applying blocking voltages to the transfer gate conductor members in said even column in rows other than said one row for inhibiting the transfer of charge in the charge storage regions underlying rows of source and receiver conductor members other than said one row.

Claim 27

A semiconductor device comprising a substrate of semiconductor material of one conductivity type, a plurality of source and receiver conductor members insulatingly overlying said substrate, a plurality of transfer gate conductor members insulatingly overlying said substrate, each spaced between adjacent source and receiver conductor members, said source and receiver conductor members being arranged in a plurality of rows and a plurality of columns, the conductor members in odd columns being conductively interconnected and the conductor members in even columns being conductively interconnected, said transfer gate conductor members being arranged in a plurality of rows and a plurality of columns, in each of the rows the conductor members located in odd columns being interconnected and the conductor members located in even columns being interconnected, means applying a fixed bias voltage to said source and receiver conductor members to establish storage regions in said substrate underlying said conductor members, means applying a first voltage of one phase to the source and receiver conductor members in the odd columns to form first charge storage regions in said substrate, means applying a second voltage of the opposite phase to the source and receiver conductor members in the even columns to form second charge storage regions in said one conductivity substrate, said second charge storage regions being spaced from said first charge storage regions to form a plurality of barrier regions within said one conductivity substrate each underlying a respective one of said transfer gate conductor members, means selectively applying a pair of oppositely phased control voltages to a row of said transfer gate conductor members, one of said control voltages being applied to the transfer gate conductor members in odd columns for alternately lowering the potentials of corresponding barrier regions to permit charge transfer thereacross and the other of said voltages being applied to the transfer gate conductor members in the even columns for alternately lowering the potentials of corresponding barrier regions to permit charge transfer thereacross, said pair of oppositely phased voltages being synchronized with said first and second voltages, whereby charge is selectively transferred in the charge storage regions in the row of source and receiver conductor members associated with said row of transfer gate conductor members, means applying blocking voltages to the transfer gate conductor members in said even column in rows other than said one row for inhibiting the transfer of charge in the charge storage regions underlying rows of source and receiver conductor members other than said one row.

Claim 28

The semiconductor device of claim 17 wHerein electrical charges are introduced by electromagnetic radiation incident on said substrate.