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US3902164A
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Method and means for reducing the amount of address translation in a virtual memory data processing system
Assignee: International Business Machines Corp
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Filing: 1973-11-30
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Granted: 1975-08-26
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Expires: 1993-11-30
Abstract
Abstract In a data processing system including an associative store for rapid translation of recently used virtual page addresses to corresponding real page addresses to access main store, an additional storage means is provided to hold data representative of a boundary in main store below which translation is not required, i.e. the virtual address is used to access this lower part of main store. This lower part of main store is often referred to as the ''''nucleus''''; and selected parts of the ''''operating system'''' and selected data are held in this area during normal machine operation. The additional storage means significantly improves system performance with a minimum increment in cost by minimizing the amount of loading and unloading of the associative translation storage means. High frequency of use instructions and data are preferably assigned the virtual addresses below said boundary.
Inventors
- 👤 Warren J Kelley
- 👤 Lawrence E Larson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 10:03
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/10; G06F12/1027
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
153 words
In a data processing system of the type in which data words are individually assigned virtual addresses from a very large virtual addressing set, and wherein a main memory is addressed by a relatively small set of real addresses, said virtual address set including virtual addresses requiring translation to real addresses prior to their use in accessing main memory, said system including an address translation means which stores recently translated virtual addresses and their corresponding real addresses, the improvement comprising, storage means for storing first data representing a selected group of virtual addresses each of which equals the corresponding reaL address, comparison means for comparing said first data with each virtual address provided by the processor, and means for disabling said address translation means and for directly using a particular address provided by the processor to address main store when the comparison means determines said particular virtual address is in said selected group.
Claim 2
Dependent Claim
153 words
In a data processing system of the type in which data words are individually assigned virtual addresses from a very large virtual addressing set, and wherein a main memory is addressed by a relatively small set of real addresses, said virtual address set including virtual addresses requiring translation to real addresses prior to their use in accessing main memory, said system including an address translation means which stores recently translated virtual addresses and their corresponding real addresses, the improvement comprising, storage means for storing first data representing a selected group of virtual addresses each of which equals the corresponding reaL address, comparison means for comparing said first data with each virtual address provided by the processor, and means for disabling said address translation means and for directly using a particular address provided by the processor to address main store when the comparison means determines said particular virtual address is in said selected group.
Claim 3
Dependent Claim
247 words
In a data processing system having a main memory, said main memory having a certain number of memory locations, memory addressing apparatus for accessing said memory with a very large set of addresses, said very large set of addresses being larger than said certain number of memory locations, said very large set of addresses including a small set of addresses each of which corresponds to one specific memory location in a small portion of said memory, said memory accessing apparatus including, a memory address register means for storing addresses and for accessing the memory location indicated by the addresses stored therein, first means which provides addresses included in said very large set of addresses, determining means for determining if the addresses provided by said first means are in said small set of addresses, translation means for translating each address which is not a member of said small set of addresses to an address which indicates one of said certain memory locations outside said small portion of memory, means responsive to said determining means for gating the address provided by said first means to said memory address provided by said first means to said memory address register means if said determining means finds that an address is included in said small set of addresses, and means for gating the address provided by said translation means to said memory address register means if the address provided to the first means is not included in said small set of addresses.
Claim 4
Dependent Claim
247 words
In a data processing system having a main memory, said main memory having a certain number of memory locations, memory addressing apparatus for accessing said memory with a very large set of addresses, said very large set of addresses being larger than said certain number of memory locations, said very large set of addresses including a small set of addresses each of which corresponds to one specific memory location in a small portion of said memory, said memory accessing apparatus including, a memory address register means for storing addresses and for accessing the memory location indicated by the addresses stored therein, first means which provides addresses included in said very large set of addresses, determining means for determining if the addresses provided by said first means are in said small set of addresses, translation means for translating each address which is not a member of said small set of addresses to an address which indicates one of said certain memory locations outside said small portion of memory, means responsive to said determining means for gating the address provided by said first means to said memory address provided by said first means to said memory address register means if said determining means finds that an address is included in said small set of addresses, and means for gating the address provided by said translation means to said memory address register means if the address provided to the first means is not included in said small set of addresses.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-08-25 | 1979-02-24 | 1979-08-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-08-25 | 1983-02-24 | 1983-08-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-08-25 | 1987-02-24 | 1987-08-26 | $7700.00 | Window Closed / Lapsed |