US3900943A
Expired / Lapsed
US
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Silicon semiconductor device array and method of making same
Assignee: Dow Silicones Corp
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Filing: 1973-06-07
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Granted: 1975-08-26
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Expires: 1993-06-07
Abstract
Abstract Silicon semiconductor device array, e.g. solar cell device or array of devices; formed from bulk silicon deposited in the form of columnar crystallites bounded by substantially vertical grain boundaries. Junctions are formed across crystallites and along grain boundaries. The grain boundaries are made substantially non-conductive by diffusion from one side of the sheet. P and n layers are provided as contact areas for electrodes. Deposition of silicon takes place directly from decomposition of siliconcontaining vapors onto a non-silicon substrate sheet.
Inventors
- 👤 Erhard Sirtl
- 👤 Cedric G Currin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 19:56
CPC Classifications
C; C30; C30B; C30B29/00; C30B29/02; C30B29/06; C30B25/00; C30B25/02; H; H10; H10D; H10D62/00; H10D62/40; H10D99/00; H10F; H10F77/00; H10F77/10; H10F77/16; H10F77/162; H10F77/164; H10F77/1642; H10F99/00; H10P; H10P14/00; H10P14/20; H10P14/24; H10P14/29; H10P14/2901; H10P14/34; H10P14/3402; H10P14/3404; H10P14/3411; Y; Y02; Y02E; Y02E10/00; Y02E10/50; Y02E10/546; Y10; Y10S; Y10S117/00; Y10S117/914; Y10S148/00; Y10S148/054; Y10S148/068; Y10S148/115; Y10S148/12; Y10S148/122; Y10S148/135; Y10S148/15
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
252 words
A METHOD OF MAKING LARGE AREA SILICON SEMICONDUCTOR DEVICES HAVING A P-N JUNCTIONS, SAID METHOD COMPRISING: PROVIDING A SHEET OF S2LIOCN OF ONE CONDUCTIVITY TYPE, SAID SHEET HAVING A LAYER OF COLUMNAR SILICON MONOCRYSTALS DEFINED BY GENERALLY VERTICAL GRAIN BOUNDARIES EXTENDING AT LEAST HALF THE THICKNESS OF SAID SHEET FROM ONE SURFACE THEREOF, SAID SHEET HAVING AN ELECTRICALLY CONDUCTIVE VOLUME IN OHMIC CONTACT WITH THE OTHER SURFACE OF THE MONOCRYSTALLINE MATERIAL DEFINED BY SAID LAYER, DIFFUSING A DIPANT OF THE OPPOSITE CONDUCTIVIEY TUPE INTO SAID ONE SURFACE OF SAID SHEET IN SUFFICIENT DEPTH TO CAUSE THE DOPANT TO DIFFUSE INTO SAID SURFACE AND ALONG PORTIONS OF SAID VERTICAL GRAIN BOUNDARIES CREATING A VOLUME OF SAID OPPOSITE CONDUCTIVITY ALONG SAID SURFACE AND ALONG PORTIONS OF SAID GRAIN BOUNDARIES THEREBY CREATING BOTH PLANAR AND VERITICAL P-N JUNCTIONS BETWEEN DIFFUSED AND UNDIFFUSED VOLUMES OF SAID SHEET, AND APPLYING AN ELECTRODE PATTERN INTERCONNECTING AREAS OF LIKE CONDUCTIVITY TYPE TO FORM A SEMICONDUCTOR DEVICE ARRAY BY A METHOD WHICH COMPRISES MASKING THE SURFACE OF SAID SILICON SHEET IN A PREDETERMINED PATTERN, AND APPLYING METALLIC CONDUCTION MATERIAL TO THE OPENSPACES IN SAID MASK, SAID METHOD OF FORMING SAID SHEET COMPRISING THE STEPS OF VAPOR DEPOSITING A LAYER OF POLYCRYSTALLINE SILICON ON A SUBSTRATE SHEET, CONVERTING SAID POLYCRYSTALLINE SILICON TO A LOW ELECTRICAL RESISTIVITY BY DOPING HEAVILY WITH A DOPANT OF KNOWN CONDUCTIVITY TYPE, AND THEN VAPOR DEPOSITING HIGH RESISTIVITY SEMICONDUCTOR SILICON OF SAID KNOWN CONDUCTIVITY TYPE IN DENSE COLUMNAR FORM TO FORM SAID SHEET HAVING VERTICAL GRAIN BOUNDARIES.
Claim 2
Independent Claim
252 words
A METHOD OF MAKING LARGE AREA SILICON SEMICONDUCTOR DEVICES HAVING A P-N JUNCTIONS, SAID METHOD COMPRISING: PROVIDING A SHEET OF S2LIOCN OF ONE CONDUCTIVITY TYPE, SAID SHEET HAVING A LAYER OF COLUMNAR SILICON MONOCRYSTALS DEFINED BY GENERALLY VERTICAL GRAIN BOUNDARIES EXTENDING AT LEAST HALF THE THICKNESS OF SAID SHEET FROM ONE SURFACE THEREOF, SAID SHEET HAVING AN ELECTRICALLY CONDUCTIVE VOLUME IN OHMIC CONTACT WITH THE OTHER SURFACE OF THE MONOCRYSTALLINE MATERIAL DEFINED BY SAID LAYER, DIFFUSING A DIPANT OF THE OPPOSITE CONDUCTIVIEY TUPE INTO SAID ONE SURFACE OF SAID SHEET IN SUFFICIENT DEPTH TO CAUSE THE DOPANT TO DIFFUSE INTO SAID SURFACE AND ALONG PORTIONS OF SAID VERTICAL GRAIN BOUNDARIES CREATING A VOLUME OF SAID OPPOSITE CONDUCTIVITY ALONG SAID SURFACE AND ALONG PORTIONS OF SAID GRAIN BOUNDARIES THEREBY CREATING BOTH PLANAR AND VERITICAL P-N JUNCTIONS BETWEEN DIFFUSED AND UNDIFFUSED VOLUMES OF SAID SHEET, AND APPLYING AN ELECTRODE PATTERN INTERCONNECTING AREAS OF LIKE CONDUCTIVITY TYPE TO FORM A SEMICONDUCTOR DEVICE ARRAY BY A METHOD WHICH COMPRISES MASKING THE SURFACE OF SAID SILICON SHEET IN A PREDETERMINED PATTERN, AND APPLYING METALLIC CONDUCTION MATERIAL TO THE OPENSPACES IN SAID MASK, SAID METHOD OF FORMING SAID SHEET COMPRISING THE STEPS OF VAPOR DEPOSITING A LAYER OF POLYCRYSTALLINE SILICON ON A SUBSTRATE SHEET, CONVERTING SAID POLYCRYSTALLINE SILICON TO A LOW ELECTRICAL RESISTIVITY BY DOPING HEAVILY WITH A DOPANT OF KNOWN CONDUCTIVITY TYPE, AND THEN VAPOR DEPOSITING HIGH RESISTIVITY SEMICONDUCTOR SILICON OF SAID KNOWN CONDUCTIVITY TYPE IN DENSE COLUMNAR FORM TO FORM SAID SHEET HAVING VERTICAL GRAIN BOUNDARIES.
Claim 3
Dependent Claim
15 words
A method as defined in claim 1 wherein said substrate sheet is an electrical insulator.
Claim 4
Dependent Claim
15 words
A method as defined in claim 1 wherein said substrate sheet is an electrical conductor.
Claim 5
Dependent Claim
26 words
A method as defined in claim 1 wherein said substrate sheet has a surface of silicon carbide provided on portions thereof on which silicon is deposited.
Claim 6
Dependent Claim
27 words
A method as defined in claim 1 wherein a metallic or oxide layer is provided on the deposition side of said substrate sheet for gettering heavy impurities.
Claim 7
Dependent Claim
57 words
A method as defined in claim 1 wherein said vapor deposition of polycrystalline silicon is accomplished by exposing said substrate to chlorosilane or silane carried in a hydrogen stream while said substrate is heated to a temperature between 900*C. and 1200*C. and continuing said exposure until said deposition reaches a thickness of between 50 and 500 microns.
Claim 8
Dependent Claim
60 words
A method as defined in claim 6 wherein trichlorosilane is used and the trichlorosilane to hydrogen ratio in said hydrogen stream is between 0.5 and 10 mole percent and said substrate is subjected to said stream for 3 to 10 minutes at a temperature below 1025*C. and then for an additional 25 to 100 minutes at a temperature above 1025*C.
Claim 9
Dependent Claim
18 words
A method as defined in claim 1 wherein said large area silicon semiconductor devices are solar cell arrays.
Claim 10
Independent Claim
224 words
A method of making large area silicon semiconductor devices having p-n junctions, said method comprising: providing a sheet of silicon of one conductivity type, said sheet having a layer of columnar silicon monocrystals defined by generally vertical grain boundaries extending at least half the thickness of said sheet from one surface thereof, said sheet having an electrically conductive volume in ohmic contact with the other surface of the monocrystalline material defined by said layer; diffusing a dopant of the opposite conductivity type into said one surface of said sheet in sufficient depth to cause the dopant to diffuse into said surface and along portions of said vertical grain boundaries creating a Volume of said opposite conductivity along said surface and along portions of said grain boundaries thereby creating both planar and vertical p-n junctions between diffused and undiffused volumes of said sheet, and applying an electrode pattern interconnecting areas of like conductivity type to form a semiconductor device array, said method of forming said sheet comprising the steps of vapor depositing a layer of polycrystalline silicon on a substrate sheet, converting said polycrystalline silicon to a low electrical resistivity by doping heavily with a dopant of known conductivity type, and then vapor depositing high resistivity semiconductor silicon of said known conductivity type in dense columnar form to form said sheet having vertical grain boundaries.
Claim 11
Independent Claim
224 words
A method of making large area silicon semiconductor devices having p-n junctions, said method comprising: providing a sheet of silicon of one conductivity type, said sheet having a layer of columnar silicon monocrystals defined by generally vertical grain boundaries extending at least half the thickness of said sheet from one surface thereof, said sheet having an electrically conductive volume in ohmic contact with the other surface of the monocrystalline material defined by said layer; diffusing a dopant of the opposite conductivity type into said one surface of said sheet in sufficient depth to cause the dopant to diffuse into said surface and along portions of said vertical grain boundaries creating a Volume of said opposite conductivity along said surface and along portions of said grain boundaries thereby creating both planar and vertical p-n junctions between diffused and undiffused volumes of said sheet, and applying an electrode pattern interconnecting areas of like conductivity type to form a semiconductor device array, said method of forming said sheet comprising the steps of vapor depositing a layer of polycrystalline silicon on a substrate sheet, converting said polycrystalline silicon to a low electrical resistivity by doping heavily with a dopant of known conductivity type, and then vapor depositing high resistivity semiconductor silicon of said known conductivity type in dense columnar form to form said sheet having vertical grain boundaries.
Claim 12
Dependent Claim
15 words
A method as defined in claim 9 wherein said substrate sheet is an electrical insulator.
Claim 13
Dependent Claim
15 words
A method as defined in claim 9 wherein said substrate sheet is an electrical conductor.
Claim 14
Dependent Claim
26 words
A method as defined in claim 9 wherein said substrate sheet has a surface of silicon carbide provided on portions thereof on which silicon is deposited.
Claim 15
Dependent Claim
27 words
A method as defined in claim 9 wherein a metallic or oxide layer is provided on the deposition side of said substrate sheet for gettering heavy impurities.
Claim 16
Dependent Claim
57 words
A method as defined in claim 9 wherein said vapor deposition of polycrystalline silicon is accomplished by exposing said substrate to chlorosilane or silane carried by a hydrogen stream while said substrate is heated to a temperature between 900*C. and 1200*C. and continuing said exposure until said deposition reaches a thickness of between 50 and 500 microns.
Claim 17
Dependent Claim
60 words
A method as defined in claim 9 wherein trichlorosilane is used and the trichlorosilane to hydrogen ratio in said hydrogen stream is between 0.5 and 10 mole percent and said substrate is subject to said stream for 3 to 10 minutes at a temperature below 1025*C. and then for an additional 25 to 100 minutes at a temperature above 1025*C.
Claim 18
Dependent Claim
18 words
A method as defined in claim 9 wherein said large area silicon semiconductor devices are solar cell arrays.
References Cited (Backward Citations)
US3651385A
Cited
US3725751A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-08-25 | 1979-02-24 | 1979-08-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-08-25 | 1983-02-24 | 1983-08-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-08-25 | 1987-02-24 | 1987-08-26 | $7700.00 | Window Closed / Lapsed |