Patent US3900837A successfully refreshed from Google Patents.
US3900837A
Expired / Lapsed
US
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Variably addressable semiconductor mass memory
Assignee: Bull HN Information Systems Italia SpA
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Filing: 1974-02-04
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Granted: 1975-08-19
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Expires: 1994-02-04
Abstract
Abstract A block-addressable mass memory subsystem comprising wafer-size modules of LSI semiconductor basic circuits is disclosed. The basic circuits are interconnected on the wafer by non-unique wiring bus portions formed in a universal pattern as part of each basic circuit. A disconnect circuit isolates defective basic circuits from the bus. A variable address storage register is provided for each basic circuit. An inhibit chain interconnects all of the basic circuits, whereby one and only one basic circuit is responsive to store a unique address in its address storage register.
Inventors
- 👤 John C Hunter
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 11:19
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/78; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G11C29/83; G11C29/832; G11C8/00; G11C8/12
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
389 words
An integrated-circuit store having connected thereto from an external source means for transmitting an address signal, means for transmitting a data signal, and means for transmitting at least one control signal and adapted to receive address and control signals from said external source and to transfer data signals to and from said external source, said store comprising a body of semiconductor material, a plurality of basic circuits formed on said body of semiconductor material as a common substrate, and means for connecting said transmitting means to at least one of said plurality of basic circuits, each one of said basic circuits comprising: a bus portion including at least one address signal line, a data signal line, and a plurality of control signal lines, said bus portion interconnecting said plurality of basic circuits; first means for storing said data signals; second means for storing an address; third means for storing at least one status signal; means responsive to said third storage means for selectively enabling said second storage means to store a unique address transmitted over said address signal line; fourth means for selectively inhibiting the operation of said enabling means, said fourth means being responsive to the contents of said third means and to an inhibit control signal transmitted over a predetermined one of said control signal lines; fifth means, associated with said predetermined control signal line, for ordering said one basic circuit relative to the other basic circuits of said integrated-circuit store, said fifth means being responsive to the contents of all of said third means of the basic circuits of higher order than said one basic circuit to selectively generate said inhibit control signal over said predetermined control signal line to the basic circuits of lower order; means for controlling the transfer of dtat signals between said data signal line and said first storage means; means responsive to a comparison between address signals received over said at least one address signal line and said stored address for actuating said controlling means; second means for connecting said at least one address signal line to said actuating means, for connecting said data signal line to said first storage means, and for connecting said control signal lines to said third storage means; and means for disabling said second connecting means, thereby disconnecting said one basic circuit from said signal bus.
Claim 2
Dependent Claim
389 words
An integrated-circuit store having connected thereto from an external source means for transmitting an address signal, means for transmitting a data signal, and means for transmitting at least one control signal and adapted to receive address and control signals from said external source and to transfer data signals to and from said external source, said store comprising a body of semiconductor material, a plurality of basic circuits formed on said body of semiconductor material as a common substrate, and means for connecting said transmitting means to at least one of said plurality of basic circuits, each one of said basic circuits comprising: a bus portion including at least one address signal line, a data signal line, and a plurality of control signal lines, said bus portion interconnecting said plurality of basic circuits; first means for storing said data signals; second means for storing an address; third means for storing at least one status signal; means responsive to said third storage means for selectively enabling said second storage means to store a unique address transmitted over said address signal line; fourth means for selectively inhibiting the operation of said enabling means, said fourth means being responsive to the contents of said third means and to an inhibit control signal transmitted over a predetermined one of said control signal lines; fifth means, associated with said predetermined control signal line, for ordering said one basic circuit relative to the other basic circuits of said integrated-circuit store, said fifth means being responsive to the contents of all of said third means of the basic circuits of higher order than said one basic circuit to selectively generate said inhibit control signal over said predetermined control signal line to the basic circuits of lower order; means for controlling the transfer of dtat signals between said data signal line and said first storage means; means responsive to a comparison between address signals received over said at least one address signal line and said stored address for actuating said controlling means; second means for connecting said at least one address signal line to said actuating means, for connecting said data signal line to said first storage means, and for connecting said control signal lines to said third storage means; and means for disabling said second connecting means, thereby disconnecting said one basic circuit from said signal bus.
Claim 3
Dependent Claim
16 words
An integrated-circuit store according to claim 1 wherein said disabling means comprises a semipermanent voltage-programmable transistor.
Claim 4
Dependent Claim
409 words
An integrated-circuit store having applied thereto from a controller a plurality of address and control signals and connected to an external data line and adapted to transfer data signals to and from said external data line, said store comprising a body of semiconductor material, a plurality of basic circuits formed on said body of semiconductor material as a common substrate, and a first means for connecting said data line and said applied signals to at least one of said pLurality of basic circuits, each one of said basic circuits comprising: a bus portion including a plurality of address and control signal lines and a data signal line, said bus portion abutting a like adjacent bus portion to form therewith a signal bus interconnecting said plurality of basic circuits; switching means; first means for storing said data signals; second means for storing an address; third means for storing a status signal, said third means including enabling means responsive to said status signal for selectively enabling said second storage means to store a unique address transmitted over said address signal lines; fourth means for selectively inhibiting the operation of said enabling means, said fourth means being responsive to the contents of said third means and to an inhibit control signal transmitted over a predetermined one of said control signal lines; fifth means, associated with said predetermined control signal line, for ordering said one basic circuit relative to the other basic circuits of said integrated-circuit store, said fifth means being responsive to the contents of all of said third means of the basic circuits of higher order than said one basic circuit to selectively generate said inhibit control signal over said predetermined control signal line to the basic circuits of lower order; means for comparing said address signals with the contents of said second storage means, said comparing means being responsive to a coincidence between said address signals and said unique stored address to generate a control enable signal; means connected to said first storage means and responsive to said control enable signal to control the transfer of said data signals between said data signal line and said first storage means; second means for connecting via said switching means said address signals to said comparing means, said control signals to said fourth and fifth means, and said data signal line to said first storage means; and means for disabling said switching means, thereby disconnecting said one basic circuit from said signal bus.
Claim 5
Dependent Claim
409 words
An integrated-circuit store having applied thereto from a controller a plurality of address and control signals and connected to an external data line and adapted to transfer data signals to and from said external data line, said store comprising a body of semiconductor material, a plurality of basic circuits formed on said body of semiconductor material as a common substrate, and a first means for connecting said data line and said applied signals to at least one of said pLurality of basic circuits, each one of said basic circuits comprising: a bus portion including a plurality of address and control signal lines and a data signal line, said bus portion abutting a like adjacent bus portion to form therewith a signal bus interconnecting said plurality of basic circuits; switching means; first means for storing said data signals; second means for storing an address; third means for storing a status signal, said third means including enabling means responsive to said status signal for selectively enabling said second storage means to store a unique address transmitted over said address signal lines; fourth means for selectively inhibiting the operation of said enabling means, said fourth means being responsive to the contents of said third means and to an inhibit control signal transmitted over a predetermined one of said control signal lines; fifth means, associated with said predetermined control signal line, for ordering said one basic circuit relative to the other basic circuits of said integrated-circuit store, said fifth means being responsive to the contents of all of said third means of the basic circuits of higher order than said one basic circuit to selectively generate said inhibit control signal over said predetermined control signal line to the basic circuits of lower order; means for comparing said address signals with the contents of said second storage means, said comparing means being responsive to a coincidence between said address signals and said unique stored address to generate a control enable signal; means connected to said first storage means and responsive to said control enable signal to control the transfer of said data signals between said data signal line and said first storage means; second means for connecting via said switching means said address signals to said comparing means, said control signals to said fourth and fifth means, and said data signal line to said first storage means; and means for disabling said switching means, thereby disconnecting said one basic circuit from said signal bus.
Claim 6
Dependent Claim
16 words
An integrated-circuit store according to claim 3, wherein said disabling means comprises a programmable connective device.
Claim 7
Dependent Claim
16 words
An integrated-circuit store according to claim 3, wherein said disabling means comprises a semipermanent voltage-programmable transistor.
Claim 8
Dependent Claim
14 words
An integrated-circuit store according to claim 3, wherein said disabling means comprises a fuse.
Claim 9
Dependent Claim
16 words
An integrated-circuit store according to claim 1 wherein said disabling means comprises a programmable connective device.
Claim 10
Dependent Claim
14 words
An integrated-circuit store according to claim 1 wherein said disabling means comprises a fuse.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-08-18 | 1979-02-17 | 1979-08-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-08-18 | 1983-02-17 | 1983-08-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-08-18 | 1987-02-17 | 1987-08-19 | $7700.00 | Window Closed / Lapsed |