Patent US3900836A successfully refreshed from Google Patents.
US3900836A
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Interleaved memory control signal handling apparatus using pipelining techniques
Assignee: International Business Machines Corp
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Filing: 1973-11-30
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Granted: 1975-08-19
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Expires: 1993-11-30
Abstract
Abstract This specification discloses an interleaved memory in which different storage units within the memory can be operated in overlapping operating cycles to increase the apparent speed of the memory. These storage units each have a separate ring counter that is started when the particular storage unit is first accessed. The ring counter generates gating and drive pulses for the accessed storage unit at times consistent with the proper operation of that storage unit. The data to control the function performed by the memory is fed into shift registers operated in synchronism with the ring counters. In this way the data is accessible at different times at different locations along the length of the shift registers so that it is available to direct the functioning of the storage unit at times determined by the generation of the gating and timing pulses by the ring counter.
Inventors
- 👤 George P Salvo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 23:51
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/16; G06F13/1605; G06F13/1647
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
233 words
In an interleaved memory having a plurality of storage units each of which internally uses a plurality of timed operating pulses that are generated by a separate ring counter driven by a clocking source which determines the intervals at which the storage units can be operated, an improved storage control unit comprising: a. a plurality of multi stage shift registers driven by said clocking source for receiving control information for instructing the memory to perform either a fetch, store or partial store operation; b. means for supplying a control signal to at least the ring counter supplying operating pulses to the storage unit of interleaved memory being accessed and to the shift registers to start the ring counter and the shift registers so that as a result of the shift registers being driven by the same clocking source as the ring counter the shift registers and ring counter operate in synchronism; and c. logic means coupling inputs of the memory units to selected stages in first plurality of shift registers for generating control signals that permit the passage of data into the accessed memory unit only at those times that the control signals generated from the control information in the selected stages of the plurality of shift registers indicates data should be entered into the accessed memory unit of the interleaved memory to perform one of the fetch, store or partial store operations.
Claim 2
Dependent Claim
233 words
In an interleaved memory having a plurality of storage units each of which internally uses a plurality of timed operating pulses that are generated by a separate ring counter driven by a clocking source which determines the intervals at which the storage units can be operated, an improved storage control unit comprising: a. a plurality of multi stage shift registers driven by said clocking source for receiving control information for instructing the memory to perform either a fetch, store or partial store operation; b. means for supplying a control signal to at least the ring counter supplying operating pulses to the storage unit of interleaved memory being accessed and to the shift registers to start the ring counter and the shift registers so that as a result of the shift registers being driven by the same clocking source as the ring counter the shift registers and ring counter operate in synchronism; and c. logic means coupling inputs of the memory units to selected stages in first plurality of shift registers for generating control signals that permit the passage of data into the accessed memory unit only at those times that the control signals generated from the control information in the selected stages of the plurality of shift registers indicates data should be entered into the accessed memory unit of the interleaved memory to perform one of the fetch, store or partial store operations.
Claim 3
Dependent Claim
152 words
The memory of claim 1 wherein said plurality of shift registers includes three shift registers each storing one binary digit in each stage thereof, wherein: the first shift register stores a select digit indicating the selection of one of the memory units for accessing when a binary 1 is stored therein; the second shift register stores a store digit indicating the performance of a write operation is to be performed when a binary 1 is stored therein; the third digit stores a partial store digit indicating only part of the data has to be rewritten during the store operation when a binary 1 is stored therein; and the three shift registers together indicate a write operation is to be performed when there is a binary 1 stored in any given stage of the first shift register and a binary 0 stored in the corresponding stages of the second and third shift registers.
Claim 4
Dependent Claim
72 words
The memory of claim 2 wherein said plurality of shift registers includes additional shift registers, the first two of which store data indicating that the operation performed by the memory as controlled by the data in the corresponding stages of said three shift registers may have to be aborted and the remainder of said additional shift registers indicating which bytes are to be written into the memory during a partial store operation.
Claim 5
Dependent Claim
67 words
The memory of claim 2 including first logic means to feed the selection digits to the ring counter of the selected storage unit during one time period; and second logic means coupling an intermediate output of the shift registers receiving the select signals to the input of the storage units to control which of the storage units receives the data on a store and partial store operation.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-08-18 | 1979-02-17 | 1979-08-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-08-18 | 1983-02-17 | 1983-08-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-08-18 | 1987-02-17 | 1987-08-19 | $7700.00 | Window Closed / Lapsed |