US3900352A
Expired / Lapsed
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Isolated fixed and variable threshold field effect transistor fabrication technique
Assignee: International Business Machines Corp
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Filing: 1973-11-01
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Granted: 1975-08-19
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Expires: 1993-11-01
Abstract
Abstract This describes a process for producing both fixed and variable threshold devices in a single semi-conductor array without critical alignment of masks especially between sequential etching and diffusion steps. This process uses a series of insulating layers on a semiconductor body, each layer being etched by a process different from that required to attach any adjacent contiguous layer, a masking operation to initially define all the devices to be ultimately created and applying a series of coatings to permit the sequential selective forming of both fixed and variable threshold devices in the array. In essence, this invention teaches that multi-level dielectrics having different etching characteristics can be used in a manner such that the first of the layers will have produced therein all the subsequent steps and devices to be produced in the underlying body and will serve to limit the subsequent etching and/or diffusion steps.
Inventors
- 👤 Michael David Potter
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 05:44
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0144; H10D84/02; H10D84/03; H10D84/038; H10D84/8314; Y; Y10; Y10S; Y10S148/00; Y10S148/043; Y10S148/085
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
201 words
A METHOD OF FABRICATING A VARIABLE THRESHOLD FIELD EFFECT TRANSISTOR HAVING SOURCE DRAIN AND GATE REGIONS AND A FIXED THRESHOLD FIELD EFFECT TRANSISTOR HAVING SOURCE, DRAIN AND GATE REGIONS IN THE SAME SEMICONDUCTOR BODY WITH AN ISOLATION REGION BETWEEN THE DEVICES COMPRISING THE STEPS OF DEPOSITING ON THE SEMICONDUCTOR BODY A SERIES OF INSULATING LAYERS, ADJACENT LAYERS HAVING DIFFERENT ETCH RATIOS, DEPOSITING A FIRST MASK ON SAID LAYERS WHICH DEFINES THE SOURCE, DRAIN, AND GATE REGIONS OF BOTH A FIXED THRESHOLD FIELD EFFECT TRANSISTOR AND A VARIABLE THRESHOLD FIELD EFFECT TRANSISTOR, SELECTIVELY ETCHING SELECTED ONES OF SAID LAYERS THROUGH SAID MASK TO DELINEATE THE SOURCE, DRAIN, AND GATE REGIONS OF THE TRANSISTORS DEFINED BY SAID MASK IN SAID SELECTED LAYERS TO SELECTIVELY EXPOSE SURFACE PORTIONS OF THE BODY, SELECTIVELY INTRODUCING IMPURITIES INTO THE EXPOSED SURFACE PORTIONS OF THE BODY TO CREATE SEPARATED DIFFUSIONS IN THE BODY, MASKING THE GATE REGION OF THE VARIABLE THRESHOLD TRANSISTOR, SELECTIVELY REMOVING THE INSULATING LAYERS IN THE GATE REGION OF THE FIXED THRESHOLD TRANSISTOR, GROWING A GATE OXIDE IN THE GATE REGION OF THE FIXED THRESHOLD TRANSISTOR, AND FORMING ELECTRODES ON SAID FIDDUSIONS AND OVER THE GATE REGIONS OF SAID FIXED THRESHOLD AND VARIABLE THRESHOLD TRANSISTORS.
Claim 2
Independent Claim
201 words
A METHOD OF FABRICATING A VARIABLE THRESHOLD FIELD EFFECT TRANSISTOR HAVING SOURCE DRAIN AND GATE REGIONS AND A FIXED THRESHOLD FIELD EFFECT TRANSISTOR HAVING SOURCE, DRAIN AND GATE REGIONS IN THE SAME SEMICONDUCTOR BODY WITH AN ISOLATION REGION BETWEEN THE DEVICES COMPRISING THE STEPS OF DEPOSITING ON THE SEMICONDUCTOR BODY A SERIES OF INSULATING LAYERS, ADJACENT LAYERS HAVING DIFFERENT ETCH RATIOS, DEPOSITING A FIRST MASK ON SAID LAYERS WHICH DEFINES THE SOURCE, DRAIN, AND GATE REGIONS OF BOTH A FIXED THRESHOLD FIELD EFFECT TRANSISTOR AND A VARIABLE THRESHOLD FIELD EFFECT TRANSISTOR, SELECTIVELY ETCHING SELECTED ONES OF SAID LAYERS THROUGH SAID MASK TO DELINEATE THE SOURCE, DRAIN, AND GATE REGIONS OF THE TRANSISTORS DEFINED BY SAID MASK IN SAID SELECTED LAYERS TO SELECTIVELY EXPOSE SURFACE PORTIONS OF THE BODY, SELECTIVELY INTRODUCING IMPURITIES INTO THE EXPOSED SURFACE PORTIONS OF THE BODY TO CREATE SEPARATED DIFFUSIONS IN THE BODY, MASKING THE GATE REGION OF THE VARIABLE THRESHOLD TRANSISTOR, SELECTIVELY REMOVING THE INSULATING LAYERS IN THE GATE REGION OF THE FIXED THRESHOLD TRANSISTOR, GROWING A GATE OXIDE IN THE GATE REGION OF THE FIXED THRESHOLD TRANSISTOR, AND FORMING ELECTRODES ON SAID FIDDUSIONS AND OVER THE GATE REGIONS OF SAID FIXED THRESHOLD AND VARIABLE THRESHOLD TRANSISTORS.
Claim 3
Dependent Claim
30 words
The method of claim 1 which additionally includes the step of forming a diffused isolation region between said fixed threshold field effect transistor and said variable threshold field effect transistor.
Claim 4
Dependent Claim
40 words
The method of claim 2 wherein the isolation region is formed by selectively exposing a surface portion of the body between the delineated transistors and diffusing an impurity into said body to form a rectifying junction between said delineated transistors.
Claim 5
Dependent Claim
22 words
The method of claim 3 where there is additionally provided a step of forming a thick pyrolytic oxide over said isolation regions.
Claim 6
Dependent Claim
35 words
The method of claim 1 wherein said series of insulating layers comprises a first layer of silicon dioxide on the surface of the semiconductor body coated with alternating layers of aluminum trioxide and silicon dioxide.
Claim 7
Dependent Claim
19 words
The method of claim 5 wherein said layers of aluminum trioxide are formed by a chemical vapor deposition process.
Claim 8
Dependent Claim
35 words
The method of claim 6 wherein said aluminum trioxide has a resistivity of about 1011 ohm centimeters at 5 X 106 volts per centimeter and a dielectric breakdown of 7 X 106 volts per centimeter.
Claim 9
Independent Claim
373 words
A method of fabricating variable threshold field effect transistors having source, drain, and gate regions and fixed threshold field effect transistors having source, drain, and gate regions in the same semiconductor body with an isolation region between the fixed threshold transistors and the variable threshold transistors comprising the steps of growing an epitaxial layer of a first conductivity type upon the surface of a substrate consisting of a semiconductor body of a second and opposite conductivity type, forming a first silicon oxide layer of less than 100 Angstroms in thickness on the surface of said epitaxial layer, depositing a layer of aluminum trioxide of less than 1000 Angstroms in thickness on the surface of said first silicon oxide layer, coating said layer of aluminum trioxide with alternating layers of materials each of which has an etching characteristic different from the etching characteristic of an adjacent layer, delineating the source, drain, and gate regions of both fixed threshold field effect transistors and variable threshold field effect transistors and an isolation region therebetween with a first mask, etching an isolation defining opening and source and drain openings in the uppermost of said alternating layers, through said first mask, masking said source and drain openings, extending said isolation defining opening through said aluminum trioxide layer to said first silicon oxide layer, selectively diffusing through said isolation defining opening an impurity of said second conductivity type to form a diffused isolation region in said epitaxial layer between said delineated fixed threshold transistors and Said variable threshold transistors, extending said source and drain openings through said aluminum trioxide layer to at least said first silicon oxide layer, selectively diffusing through said source and drain openings an impurity of said second conductivity type to form diffused source and drain regions for said fixed threshold transistors and said variable threshold transistors in said epitaxial layer, masking said silicon oxide layer and said aluminum trioxide layer in the gate regions of said variable threshold transistors, removing said aluminum trioxide layer over the gate regions of said fixed threshold transistors, forming a second silicon oxide layer over the gate regions of said fixed threshold transistors, and forming metallic, source, drain and gate electrodes on said fixed threshold and said variable threshold devices.
Claim 10
Independent Claim
373 words
A method of fabricating variable threshold field effect transistors having source, drain, and gate regions and fixed threshold field effect transistors having source, drain, and gate regions in the same semiconductor body with an isolation region between the fixed threshold transistors and the variable threshold transistors comprising the steps of growing an epitaxial layer of a first conductivity type upon the surface of a substrate consisting of a semiconductor body of a second and opposite conductivity type, forming a first silicon oxide layer of less than 100 Angstroms in thickness on the surface of said epitaxial layer, depositing a layer of aluminum trioxide of less than 1000 Angstroms in thickness on the surface of said first silicon oxide layer, coating said layer of aluminum trioxide with alternating layers of materials each of which has an etching characteristic different from the etching characteristic of an adjacent layer, delineating the source, drain, and gate regions of both fixed threshold field effect transistors and variable threshold field effect transistors and an isolation region therebetween with a first mask, etching an isolation defining opening and source and drain openings in the uppermost of said alternating layers, through said first mask, masking said source and drain openings, extending said isolation defining opening through said aluminum trioxide layer to said first silicon oxide layer, selectively diffusing through said isolation defining opening an impurity of said second conductivity type to form a diffused isolation region in said epitaxial layer between said delineated fixed threshold transistors and Said variable threshold transistors, extending said source and drain openings through said aluminum trioxide layer to at least said first silicon oxide layer, selectively diffusing through said source and drain openings an impurity of said second conductivity type to form diffused source and drain regions for said fixed threshold transistors and said variable threshold transistors in said epitaxial layer, masking said silicon oxide layer and said aluminum trioxide layer in the gate regions of said variable threshold transistors, removing said aluminum trioxide layer over the gate regions of said fixed threshold transistors, forming a second silicon oxide layer over the gate regions of said fixed threshold transistors, and forming metallic, source, drain and gate electrodes on said fixed threshold and said variable threshold devices.
Claim 11
Dependent Claim
32 words
The method of claim 8 wherein isolation region is extended through said epitaxial layer to said body by the step of diffusing the source and drain region impurities into said epitaxial layer.
Claim 12
Dependent Claim
31 words
The method claim 9 which additionally includes the step of forming a thick pyrolytic oxide over said isolation region and between all of said transistors to eliminate any parasitic transistor action.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-08-18 | 1979-02-17 | 1979-08-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-08-18 | 1983-02-17 | 1983-08-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-08-18 | 1987-02-17 | 1987-08-19 | $7700.00 | Window Closed / Lapsed |