Condition sensing and control apparatus

Claim 2

Digital condition sensing and control apparatus comprising a. means for sensing the condition of a variable and providing an actual condition signal in which said signal has a time duration related in magnitude to the actual condition of the variable, b. means responsive to said sensing means for generating a reference signal which is initiated at the same time as said actual condition signal, said reference signal having a time duration related in magnitude to a desired condition for said variable, c. first logic circuit means including means for providing a complementary signal of said reference signal and for further providing a first output signal in response to a coincidence of said actual condition signal and said reference complementary signal to indicate a deviation of said variable in a first direction from said desired condition for said variable, said first output signal having a time duration related in magnitude to the difference between the actual condition and the desired condition, and d. second logic circuit means including means for providing a complementary signal of said actual condition signal and for further providing a second output signal in response to a coincidence of said reference signal and said complementary actual condition signal to indicate a deviation of said variable in a second direction from said desired condition for said variable, said second output signal having a time duration related in magnitude to the difference between the actual condition and the desired condition.

Claim 3

Apparatus as defined in claim 1 a. in which said sensing means provides a continuous series of said actual condition signals and said reference signal generating means provides a continuous series of said reference signals, b. in which said first and second logic circuit means provides a first series and a second series of first output signals and second output signals in response to deviations from said desired condition in first and second directions, and c. which further includes first and second output means responsive to said first and second series of said output signals, respectively, each of said output means including stretching circuit means operable to pass output signals only in response to output signals exceeding a predetermined magnitude of time duration thereby providing a dead band on each side of said desired condition to prevent hunting.

Claim 4

Digital speed sensing apparatus comprising a. means for sensing the speed of a device and providing a series of actual speed signals in which each signal has a time duration related in magnitude to the actual speed of said device, b. means responsive to said sensing means for providing a like series of reference signals in which each of said reference signals is initiated at the same time as each of said actual speed signals and in which each of said reference signals has a time duration related in magnitude to a desired speed for said device, c. first logic circuit means responsive to the presence of an actual speed signal having a longer time duration than a concurrently occurring reference speed signal for providing a first output signal having a time duration related in magnitude to the amount the actual speed exceeds the desired speed, and d. second logic circuit means responsive to the presence of an actual speed signal having a shorter time duration than a concurrently occurring reference speed signal for providing a second output signal having a time duration related in magnitude to the amount the actual speed is lower than the desired speed.

Claim 5

Digital speed sensing apparatus comprising a. means for sensing the speed of a device and providing a series of actual speed signals in which each signal has a time duration related in magnitude to the actual speed of said device, b. means responsive to said sensing means for providing a like series of reference signals in which each of said reference signals is initiated at the same time as each of said actual speed signals and in which each of said reference signals has a time duration related in magnitude to a desired speed for said device, c. first logic circuit means responsive to the presence of an actual speed signal having a longer time duration than a concurrently occurring reference speed signal for providing a first output signal having a time duration related in magnitude to the amount the actual speed exceeds the desired speed, and d. second logic circuit means responsive to the presence of an actual speed signal having a shorter time duration than a concurrently occurring reference speed signal for providing a second output signal having a time duration related in magnitude to the amount the actual speed is lower than the desired speed.

Claim 6

Apparatus as defined in claim 3 which further includes output means operable to pass only output signals which exceed a predetermined minimum magnitude of time duration, thereby providing a dead band on each side of said desired speed to prevent a hunting operation by said speed sensing apparatus.

Claim 7

Apparatus as defined in claim 3 in which said sensing means includes a. means for generating a series of input signals having a frequency proportional to the actual speed of said device, and b. frequency divider means for reducing the number of input signals to increase the time spacing between input signals to prevent time overlaps of reference and input signals.

Claim 8

Digital control apparatus comprising a. means for sensing the condition of a variable and providing a series of digital actual condition signals in which each signal has a time duration related in magnitude to the actual Condition of the device, b. means responsive to said sensing means for generating a like series of digital reference signals in which each reference signal is initiated at the same time as each of said actual condition signals, and in which each reference signal has a time duration related in magnitude to a desired condition for said variable, c. means responsive to one of said series of actual condition and reference signals for providing a series of digital signals complementary to said one series, and d. logic circuit means responsive to the other of said series of actual condition and reference signals and to said series of complementary signals for providing a series of digital output signals each having a time duration related in magnitude to the difference between the actual and desired conditions for said variable when said other and said complementary series signals coincide.

Claim 9

Digital control apparatus comprising a. means for sensing the condition of a variable and providing a series of digital actual condition signals in which each signal has a time duration related in magnitude to the actual Condition of the device, b. means responsive to said sensing means for generating a like series of digital reference signals in which each reference signal is initiated at the same time as each of said actual condition signals, and in which each reference signal has a time duration related in magnitude to a desired condition for said variable, c. means responsive to one of said series of actual condition and reference signals for providing a series of digital signals complementary to said one series, and d. logic circuit means responsive to the other of said series of actual condition and reference signals and to said series of complementary signals for providing a series of digital output signals each having a time duration related in magnitude to the difference between the actual and desired conditions for said variable when said other and said complementary series signals coincide.

Claim 10

Digital speed sensing apparatus comprising a. means for sensing the speed of a device and providing a first series of actual speed signals in which each signal has a time duration related in magnitude to the actual speed of said device, and for providing a second series of signals which are complementary to said first series signals; b. means responsive to said sensing means for providing a third series of reference signals in which each of said third series signals is initiated simultaneously with the intiation of a first series signal and has a time duration related in magnitude to a desired speed for said device, and for providing a fourth series of signals which are complementary to said third series of signals; c. first logic means responsive to a coincidence of said first and fourth series of signals for providing a fifth series of signals in which each fifth series signal has a time duration related in magnitude to a deviation in speed in a first direction from said desired speed; and d. second logic means responsive to a coincidence of said second and third series of signals for providing a sixth series of signals in which each sixth series signal has a time duration related in magnitude to a deviation in speed in a second direction from said desired speed.

Claim 11

Digital speed sensing apparatus comprising a. means for sensing the speed of a device and providing a first series of actual speed signals in which each signal has a time duration related in magnitude to the actual speed of said device, and for providing a second series of signals which are complementary to said first series signals; b. means responsive to said sensing means for providing a third series of reference signals in which each of said third series signals is initiated simultaneously with the intiation of a first series signal and has a time duration related in magnitude to a desired speed for said device, and for providing a fourth series of signals which are complementary to said third series of signals; c. first logic means responsive to a coincidence of said first and fourth series of signals for providing a fifth series of signals in which each fifth series signal has a time duration related in magnitude to a deviation in speed in a first direction from said desired speed; and d. second logic means responsive to a coincidence of said second and third series of signals for providing a sixth series of signals in which each sixth series signal has a time duration related in magnitude to a deviation in speed in a second direction from said desired speed.

Claim 12

Apparatus as defined in claim 7 in which said second and fourth complementary series providing means comprise NOT logic circuit means.

Claim 13

Apparatus as defined in claim 8 in which said first and second logic means comprise NAND logic circuit means providing overspeed and underspeed output signals, respectively.

Claim 14

Apparatus as defined in claim 8 in which said first and second logic means comprise AND logic circuit means providing underspeed and overspeed output signals, respectively.

Claim 15

Apparatus as defined in claim 7 in which said sensing means includes a. pickup means for generating said series of input signals, each having a frequency of occurrence related to the actual speed of said device, and b. frequency divider means responsive to said input signals for reducing the number of input signals to increase the time spacing between remaining input signals.

Claim 16

Apparatus as defined in claim 11 in which said frequency divider means includes first and second dual flip flop circuit means.

Claim 17

Apparatus as defined in claim 12 in which said periodic blanking means includes a. circuit means for providing an output which is complementary to the output of said first flip flop means, and b. logic circuit means responsive to a coincidence of an output from said second flip flop means and said complementary output from said first flip flop means.

Claim 18

Apparatus as defined in claim 7 which further includes output means operable to pass only fifth and sixth series signals which exceed a predetermined minimum time duration.

Claim 19

Apparatus as defined in claim 7 which further includes output means having stretch circuit means therein for increasing the time duration of said fifth and sixth series signals to a magnitude sufficient to be within The actuating response range of controller means responsive thereto.

Claim 20

Apparatus as defined in claim 7 which further includes a. first and second output means responsive to said fifth and sixth series of signals, respectively, b. each of said output means comprising a plurality of serially connected NOT logic circuits and capacitor loading means connected to the junctions of two said NOT logic circuits.

Claim 21

Apparatus as defined in claim 16 in which each output means comprises three NOT logic circuits and in which said capacitor loading means is connected between the second and third NOT logic circuits.

Claim 22

Speed control apparatus comprising a. first means for sensing the road speed of a vehicle, b. second means for sensing the speed of an accessory device driven by the engine of the vehicle, c. circuit means selectively responsive to said first and second sensing means for generating a series of actual speed signals, each signal having a time duration related in magnitude to actual road speed and accessory speed, d. means for generating a first series of reference signals, each first series reference signal having a time duration related in magnitude to a desired maximum road speed and being initiated simultaneously with the initiation of an actual speed signal, e. means for generating a second series of reference signals, each second series reference signal having a time duration related in magnitude to a desired set point accessory speed and being initiated simultaneously with the initiation of an actual speed signal, f. first logic circuit means responsive to the presence of an actual speed signal having a longer time duration than a concurrently occurring reference speed signal for providing a first output signal having a time duration related in magnitude to the deviation between actual and reference speeds, g. second logic circuit means responsive to the presence of an actual speed signal having a shorter time duration than a concurrently occurring reference signal for providing a second output signal having a time duration related in magnitude to the deviation between actual and reference speeds, and h. switching means for selectively connecting said first sensing means to said actual speed signal circuit means, and for inhibiting the second output signal from said second logic circuit means, and for further selectively connecting said second sensing means to said actual speed signal circuit means.

Claim 23

Speed control apparatus comprising a. first means for sensing the road speed of a vehicle, b. second means for sensing the speed of an accessory device driven by the engine of the vehicle, c. circuit means selectively responsive to said first and second sensing means for generating a series of actual speed signals, each signal having a time duration related in magnitude to actual road speed and accessory speed, d. means for generating a first series of reference signals, each first series reference signal having a time duration related in magnitude to a desired maximum road speed and being initiated simultaneously with the initiation of an actual speed signal, e. means for generating a second series of reference signals, each second series reference signal having a time duration related in magnitude to a desired set point accessory speed and being initiated simultaneously with the initiation of an actual speed signal, f. first logic circuit means responsive to the presence of an actual speed signal having a longer time duration than a concurrently occurring reference speed signal for providing a first output signal having a time duration related in magnitude to the deviation between actual and reference speeds, g. second logic circuit means responsive to the presence of an actual speed signal having a shorter time duration than a concurrently occurring reference signal for providing a second output signal having a time duration related in magnitude to the deviation between actual and reference speeds, and h. switching means for selectively connecting said first sensing means to said actual speed signal circuit means, and for inhibiting the second output signal from said second logic circuit means, and for further selectively connecting said second sensing means to said actual speed signal circuit means.

Claim 24

Apparatus as defined in claim 18 in which said first and second reference signal generating means comprises a. a one-shot multivibrator responsive to said actual speed signal generating means, b. first impedance means for controlling the time duration of said first reference signals, and c. second impedance means for controlling the time duration of said second reference signals, and in which d. said switching means further includes means for selectively connecting said first impedance means to said multivibrator when said first sensing means is connected to said actual speed circuit means, and for further selectively connecting said second impedance means to said multivibrator when said second sensing means is connected to said actual speed circuit means.

Claim 25

Apparatus as defined in claim 18 in which a. said first logic circuit means includes means responsive to one of said series of actual speed and reference signals for providing a first series of signals complementary to said one series, and means responsive to the other of said series of actual speed and reference signals and to said first series of complementary signals for providing an output signal when said other and said first complementary signals coincide, and b. said second logic circuit means includes means responsive to the other of said series of actual speed and reference signals for providing a second series of signals complementary to said other series, and means responsive to said onE of said series of actual speed and reference signals and to said second series of complementary signals for providing an output when said one and said second complementary signals coincide.

Claim 26

Digital condition sensing and control apparatus comprising a. means for sensing the condition of a variable and generating a series of input signals in which each said input signal has a time duration related in magnitude to the actual condition of the variable, b. circuit means for dividing the number of said input signals by a predetermined number and increasing the time duration of the remaining input signals by a factor related to said predetermined number, c. means responsive to said sensing means for generating a series of reference signals, each of which is initiated at the same time as an associated remaining input signal, each said reference signal having a time duration related in magnitude to a desired condition for said variable, d. first logic circuit means including means for providing a complementary signal of said reference signal and for further providing a first output signal in response to a coincidence of a remaining input signal and a reference complementary signal to indicate a deviation of said variable in a first direction from said desired condition for said variable, and e. second logic circuit means including means for providing a complementary signal of a remaining input signal and for further providing a second output signal in response to a coincidence of a reference signal and said complementary remaining input signal to indicate a deviation of said variable in a second direction from said desired condition for said variable.

Claim 27

Digital condition sensing and control apparatus comprising a. means for sensing the condition of a variable and generating a series of input signals in which each said input signal has a time duration related in magnitude to the actual condition of the variable, b. circuit means for dividing the number of said input signals by a predetermined number and increasing the time duration of the remaining input signals by a factor related to said predetermined number, c. means responsive to said sensing means for generating a series of reference signals, each of which is initiated at the same time as an associated remaining input signal, each said reference signal having a time duration related in magnitude to a desired condition for said variable, d. first logic circuit means including means for providing a complementary signal of said reference signal and for further providing a first output signal in response to a coincidence of a remaining input signal and a reference complementary signal to indicate a deviation of said variable in a first direction from said desired condition for said variable, and e. second logic circuit means including means for providing a complementary signal of a remaining input signal and for further providing a second output signal in response to a coincidence of a reference signal and said complementary remaining input signal to indicate a deviation of said variable in a second direction from said desired condition for said variable.

Claim 28

Apparatus as defined in claim 21 which further includes circuit means for periodically blanking out every other one of said remaining input signals thereby providing a series of actual condition signals having a time duration related in magnitude to the actual condition of said variable with each actual condition signal being spaced in time to prevent overlap of a reference signal between the occurrence of actual condition signals, each said reference signal being initiated at the same time as each said actual condition signal.

Claim 29

Digital condition sensing and control apparatus comprising a. means for sensing the condition of a variable and generating a series of actual condition signals in which each said signal has a time duration related in magnitude to the actual condition of the variable, b. means responsive to said sensing means for generating a series of reference signals, each of which is initiated at the same time as a like actual condition signal, each said reference signal having a time duration related in magnitude to a desired condition for said variable, and c. digital logic circuit means for comparing each of said coinciding reference and actual condition signals and for providing a series of output signals each having a time duration related in magnitude to the deviation of said variable from the desired condition for said variable.

Claim 30

Digital condition sensing and control apparatus comprising a. means for sensing the condition of a variable and generating a series of actual condition signals in which each said signal has a time duration related in magnitude to the actual condition of the variable, b. means responsive to said sensing means for generating a series of reference signals, each of which is initiated at the same time as a like actual condition signal, each said reference signal having a time duration related in magnitude to a desired condition for said variable, and c. digital logic circuit means for comparing each of said coinciding reference and actual condition signals and for providing a series of output signals each having a time duration related in magnitude to the deviation of said variable from the desired condition for said variable.