Driving circuits for electronic watches

Claim 2

A driving circuit for an electronic watch comprising oscillator means for producing a high frequency time standard signal; and divider means coupled to said oscillator means to receive said time standard signal for dividing the frequency of said time standard signal to produce low frequency timing signals for time indication, said divider means including ring counter circuit means formed from MOS transistors, said ring counter circuit means being divide-by-2n ring counter means, wherein n is an integer and equal to the number of stages of said ring counter means, each of said ring counter stages having a write terminal and an output terminal, the output terminal of each of said stages other than the last stage being connected to the write terminal of the next succeeding stage; first and second control terminals having first and second control signals respectively applied thereto; means operatively coupling said first and second control terminals to each of said stages for the control thereof; and means for applying the inverse of the signal at the output terminal of the last stage to the write terminal of the first stage.

Claim 3

A driving circuit as recited in claim 1, wherein said ring counter means includes divide-by-4 ring counter means.

Claim 4

A driving circuit as recited in claim 2, wherein said ring counter means includes a plurality of said divide-by-4 ring counter means connected in cascade, said cascade connected divide-by-4 ring counter means being connected to said oscillator means for receiving said high frequency time standard signal therefrom, and for producing an intermediate frequency signal of a frequency less than 10 Hz.

Claim 5

A driving circuit as recited in claim 3, wherein said divider means includes further of said ring counter circuit means connected in cascade for receiving said intermediate signal and for producing low frequency timing signals therefrom, said low frequency timing signals including at least a 1-minute signal, a 10-minute signal, and a 1-hour signal.

Claim 6

A driving circuit as recited in claim 1, wherein each of said stages includes a complementary NOT circuit.

Claim 7

A driving circuit as recited in claim 1, wherein each of said stages includes first and second positive logic AND-NOT circuits each having first and second control gates, said first and second positive logic AND-NOT circuits being connected in parallel to define a positive logic AND-NOT-AND circuit; first and second negative logic AND-NOT circuits each having first and second control gates, said first and second negative logic AND-NOT circuits being connected in parallel to define a negative logic AND-NOT-AND circuit; electric source means, said positive and negative logic AND-NOT-AND circuits being connected in series with each other, said series connection being connected to said electric source means; a connecting point terminal defined between said positive and negative logic AND-NOT-AND circuits in said series connection; inverter circuit means having an input connected to said connecting point terminal and having an output defining the output terminal of said stage, said stage output terminal being connected to said first control gate of each of said first positive and first negative AND-NOT-AND circuits, said write terminal being connected to each of the first control gates of said second positive and second negative AND-NOT-AND circuits, said first control terminal being connected to the second control gate of said first negative AND-NOT-AND circuit and to the second control gate of said second positive AND-NOT-AND circuit, said second control terminal being connected to the second control gate of said second negative AND-NOT-AND circuits and to the second control gate of said first positive AND-NOT-AND circuit.