US3898689A
Expired / Lapsed
US
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Assignee: AT&T Inc
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Filing: 1974-08-02
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Granted: 1975-08-05
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Expires: 1994-08-02
Abstract
Abstract A bitstream encoded in the Aiken or similar self-clocking code is converted to a binary waveform with clocking by apparatus including two spaced apart sensing devices which read the bitstream, a memory circuit for storing the data content of the portion of the bitstream disposed between the sensing devices, and logic circuitry jointly responsive to the memory and sensing devices for determining the data content of the present bit. Timing information is extracted from the bitstream by another logic circuit jointly responsive to the output of one sensing device and to the memory circuit. The apparatus permits conversion independent of reading speed variations.
Inventors
- 👤 Orazio Robert Joseph D
- 👤 Gerald Steven Soloway
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 22:25
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/10; G11B20/14; G11B20/1403; G11B20/1407; G11B20/1419; G06; G06K; G06K7/00; G06K7/01; G06K7/016; G06K7/0166
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
281 words
Apparatus for reading a binary bitstream having a first level and a second level and wherein regular transitions between said first and second levels occur at the beginning and end of each bit interval and Wherein the presence or absence of irregular transitions between said first and second levels occurring intermediate the beginning and end of each of said bit intervals are representative of the data carried by said bitstream, comprising first and second sensor means spaced apart a fixed distance s and adapted to simultaneously sense the level of said bitstream thereat, detector means responsive to said first sensor means adapted to provide an indication at each of said regular and irregular transitions between said first and seond levels, memory means for determining the number of irregular transitions occurring in the portion of said bitstream between said first and second sensor means, and logic means jointly responsive to said first and second sensor means and said memory means for a. providing a first output indication if the levels sensed by said first and second means are the same and said number of irregular transitions is even, or if the levels sensed by said first and second means are different and said number of irregular transitions is odd, and b. providing a second output indication if the levels sensed by said first and second means are the same and said number of irregular transitions is odd, or if the levels sensed by said first and second means are different and said number of irregular transitions is even, wherein said memory means is jointly responsive to said detector means and said logic means for separating said regular transitions from said irregular transitions.
Claim 2
Dependent Claim
281 words
Apparatus for reading a binary bitstream having a first level and a second level and wherein regular transitions between said first and second levels occur at the beginning and end of each bit interval and Wherein the presence or absence of irregular transitions between said first and second levels occurring intermediate the beginning and end of each of said bit intervals are representative of the data carried by said bitstream, comprising first and second sensor means spaced apart a fixed distance s and adapted to simultaneously sense the level of said bitstream thereat, detector means responsive to said first sensor means adapted to provide an indication at each of said regular and irregular transitions between said first and seond levels, memory means for determining the number of irregular transitions occurring in the portion of said bitstream between said first and second sensor means, and logic means jointly responsive to said first and second sensor means and said memory means for a. providing a first output indication if the levels sensed by said first and second means are the same and said number of irregular transitions is even, or if the levels sensed by said first and second means are different and said number of irregular transitions is odd, and b. providing a second output indication if the levels sensed by said first and second means are the same and said number of irregular transitions is odd, or if the levels sensed by said first and second means are different and said number of irregular transitions is even, wherein said memory means is jointly responsive to said detector means and said logic means for separating said regular transitions from said irregular transitions.
Claim 3
Dependent Claim
32 words
The invention defined in claim 1 further including means jointly responsive to said detector and memory means for providing a series of timing pulses indicative of the width of said bit intervals.
Claim 4
Dependent Claim
44 words
The invention defined in claim 2 wherein said memory means comprises an n-1 bit shift register, wherein n is the maximum possible number of said irregular transitions that can be combined in said portion of said bitstream between said first and second sensor means.
Claim 5
Dependent Claim
32 words
The invention defined in claim 3 wherein said logic means includes n exclusive OR gates connected in chain-like fashion and an inverter output stage if m-1<s<m, where m is an odd integer.
Claim 6
Dependent Claim
264 words
Apparatus for reading a binary bitstream having a first level and a second level and wherein regular transitions between said first and second levels occur at the beginning and end of each bit interval and wherein the presence or absence of irregular transitions between said first and second levels occurring intermediate the beginning and end of each of said bit intervals are representative of the data carried by said bitstream, comprising first and second means spaced apart a fixed distance and adapted to simultaneously sense the level of said bitstream thereat, third means adapted to provide an indication of all transitions between said first and second levels, fourth means responsive to said third means and to the data output signal of said apparatus for separating said regular transitions from said irregular transitions, thereby providing an outuput timing signal, fifth means including memory means for storing the data content of the portion of said bitstream between said first and second means, data being moved through said memory means from an input point to an output point under the control of said fourth means, and sixth means jointly responsive to said first and second means and to said memory means for supplying a data signal to said input point only if a. the levels sensed by said first and second means is the same and said data content of said memory means is representative of a first condition, or, b. the levels sensed by said first and second means is different and said data content of said memory means is not representative of said first condition.
Claim 7
Dependent Claim
264 words
Apparatus for reading a binary bitstream having a first level and a second level and wherein regular transitions between said first and second levels occur at the beginning and end of each bit interval and wherein the presence or absence of irregular transitions between said first and second levels occurring intermediate the beginning and end of each of said bit intervals are representative of the data carried by said bitstream, comprising first and second means spaced apart a fixed distance and adapted to simultaneously sense the level of said bitstream thereat, third means adapted to provide an indication of all transitions between said first and second levels, fourth means responsive to said third means and to the data output signal of said apparatus for separating said regular transitions from said irregular transitions, thereby providing an outuput timing signal, fifth means including memory means for storing the data content of the portion of said bitstream between said first and second means, data being moved through said memory means from an input point to an output point under the control of said fourth means, and sixth means jointly responsive to said first and second means and to said memory means for supplying a data signal to said input point only if a. the levels sensed by said first and second means is the same and said data content of said memory means is representative of a first condition, or, b. the levels sensed by said first and second means is different and said data content of said memory means is not representative of said first condition.
Claim 8
Dependent Claim
41 words
The invention defined in claim 5 wherein said memory means includes an n-1 bit shift register, and n equals the maximum numbEr of said irregular transitions that can occur in said portion of said bitstream between said first and second means.
Claim 9
Dependent Claim
180 words
Apparatus for converting a binary bitstream having a. first and second levels b. regular transitions between said first and second levels at the beginning and end of each bit interval, and c. irregular transitions between said first and second levels intermediate said beginning and said end of said bit interval, the presence or absence of said irregular transitions being indicative of the data content of said bitstream, into a first bitstream containing only timing information and a second bitstream containing only data, comprising: first and second means adapted to simultaneously sense said binary bitstream at two locations spaced apart by a fixed number n of bit intervals, memory means for storing the data representative of the preceding n bits of said second bitstream, first logic means responsive to said memory means and said first and second sensing means for generating the present bit of said second bitstream, and second logic means for generating said first bitstream containing only timing information by separating said regular transitions from said irregular transitions in response to said first means and said first logic means.
Claim 10
Dependent Claim
180 words
Apparatus for converting a binary bitstream having a. first and second levels b. regular transitions between said first and second levels at the beginning and end of each bit interval, and c. irregular transitions between said first and second levels intermediate said beginning and said end of said bit interval, the presence or absence of said irregular transitions being indicative of the data content of said bitstream, into a first bitstream containing only timing information and a second bitstream containing only data, comprising: first and second means adapted to simultaneously sense said binary bitstream at two locations spaced apart by a fixed number n of bit intervals, memory means for storing the data representative of the preceding n bits of said second bitstream, first logic means responsive to said memory means and said first and second sensing means for generating the present bit of said second bitstream, and second logic means for generating said first bitstream containing only timing information by separating said regular transitions from said irregular transitions in response to said first means and said first logic means.
Claim 11
Dependent Claim
155 words
Apparatus for reading a binary bitstream having a first level and a second level, wherein the presence of an irregular level transition between level transitions normally occurring at the beginning and end of a bit indicates a first input data state and wherein the absence of an irregular level transition between transitions normally occurring at the beginning and end of a bit indicates a second input data state, comprising first and second sensing means spaced apart a fixed distance and adapted to simultaneously sense the level of said bitstream thereat, third means for providing an indication of all of said level transitions, fourth means responsive to said third means for separating said normally occurring transitions from said irregular transitions, and fifth means jointly responsive to said second and fourth means for generating an output bitstream having first and second output states indicative of said first input data state and said second input data state, respectively.
Claim 12
Dependent Claim
155 words
Apparatus for reading a binary bitstream having a first level and a second level, wherein the presence of an irregular level transition between level transitions normally occurring at the beginning and end of a bit indicates a first input data state and wherein the absence of an irregular level transition between transitions normally occurring at the beginning and end of a bit indicates a second input data state, comprising first and second sensing means spaced apart a fixed distance and adapted to simultaneously sense the level of said bitstream thereat, third means for providing an indication of all of said level transitions, fourth means responsive to said third means for separating said normally occurring transitions from said irregular transitions, and fifth means jointly responsive to said second and fourth means for generating an output bitstream having first and second output states indicative of said first input data state and said second input data state, respectively.
Claim 13
Dependent Claim
127 words
Apparatus for converting an input bitstream encoded in the Aiken code to a first binary bitstream containing only data and a second bitstream containing only timing information, comprising: first and second means for simultaneously sensing said input bitstream at two locations spaced apart by a fixed distance; a first logic circuit for generating the present bit of said first bitstream; a memory circuit for storing the portion of said first bitstream representative of the portion of said input bitstream disposed between said first and second sensing means; said first logic circuit being jointly responsive to said memory circuit and to said first and second sensing means; and a second logic circuit jointly responsive to said first sensing means and said memory circuit for generating said second bitstream.
Claim 14
Dependent Claim
127 words
Apparatus for converting an input bitstream encoded in the Aiken code to a first binary bitstream containing only data and a second bitstream containing only timing information, comprising: first and second means for simultaneously sensing said input bitstream at two locations spaced apart by a fixed distance; a first logic circuit for generating the present bit of said first bitstream; a memory circuit for storing the portion of said first bitstream representative of the portion of said input bitstream disposed between said first and second sensing means; said first logic circuit being jointly responsive to said memory circuit and to said first and second sensing means; and a second logic circuit jointly responsive to said first sensing means and said memory circuit for generating said second bitstream.
Claim 15
Dependent Claim
93 words
Apparatus comprising first and second sensors spaced apart a prescribed distance along an axis and responsive independently to each bit of a coded sequence of bits moved along said axis to generate first and second signals respectively, and an electronic circuit responsive to said first and second signals to generate a data stream and a separate clocking signal, said apparatus including means for applying to said circuit in each instance the second signal which corresponds to the bit of said sequence at said first sensor, for providing said data stream and clocking signal.
Claim 16
Dependent Claim
93 words
Apparatus comprising first and second sensors spaced apart a prescribed distance along an axis and responsive independently to each bit of a coded sequence of bits moved along said axis to generate first and second signals respectively, and an electronic circuit responsive to said first and second signals to generate a data stream and a separate clocking signal, said apparatus including means for applying to said circuit in each instance the second signal which corresponds to the bit of said sequence at said first sensor, for providing said data stream and clocking signal.
Claim 17
Dependent Claim
33 words
The invention defined in claim 10 wherein said last-mentioned means comprises a memory means for storing the data content of the portion of said sequence of bits between said first and second sensors.
Claim 18
Dependent Claim
120 words
Apparatus comprising first and second sensors spaceD apart a prescribed distance along an axis and responsive independently to each bit of a coded sequence of bits moved along that axis to generate first and second signals respectively, an electronic circuit responsive to said first and second signals for forming a data stream, means responsive to the output of said circuit and to said second signals which correspond in time to the data version of said coded sequence for generating a clocking signal for said data stream, and a memory means for storing the data content of the portion of said sequence of bits between said first and second sensors and providing an indication of said data content to said circuit.
Claim 19
Dependent Claim
120 words
Apparatus comprising first and second sensors spaceD apart a prescribed distance along an axis and responsive independently to each bit of a coded sequence of bits moved along that axis to generate first and second signals respectively, an electronic circuit responsive to said first and second signals for forming a data stream, means responsive to the output of said circuit and to said second signals which correspond in time to the data version of said coded sequence for generating a clocking signal for said data stream, and a memory means for storing the data content of the portion of said sequence of bits between said first and second sensors and providing an indication of said data content to said circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-08-04 | 1979-02-03 | 1979-08-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-08-04 | 1983-02-03 | 1983-08-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-08-04 | 1987-02-03 | 1987-08-05 | $7700.00 | Window Closed / Lapsed |