Patent US3898684A successfully refreshed from Google Patents.
US3898684A
Expired / Lapsed
US
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Diffusion guarded metal-oxide-silicon field effect transistors
Assignee: Motorola Solutions Inc
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Filing: 1974-08-05
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Granted: 1975-08-05
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Expires: 1994-08-05
Abstract
Abstract Metal-oxide-silicon field effect transistors (MOSFET) are shown utilizing diffusion guarding of the gate electrode of a MOSFET device and utilizing the drain of one MOSFET device as the source of the next integrally formed MOSFET device. Other types of isolation shown include the surrounding of a functional unit with a source diffusion area, and/or permanently connecting a gate electrode to a potential level for preventing signal flow past such a gate.
Inventors
- 👤 Uryon S Davidsohn
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 11:06
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/102; H10D62/112; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D99/00; H10D84/85
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
331 words
In a field effect transistor integrated circuit, the improvement comprising: a body of semiconductor material of a relatively high resistivity and first conductivity type and having an upper surface; a source region of relatively low resistivity and opposite conductivity type extending from said surface into said body; a drain region of relatively low resistivity and opposite conductivity type extending from said surface into said body, and said drain region being in spaced relationship with said source region; a plurality of gate regions positioned adjacent said drain region and between said drain region and said source region and each of said gate regions being of relatively high resistivity and first conductivity type and being fromed integrally with said body; a plurality of guard regions of said first type conductivity and lower resistivity when compared to said body extending from said surface into said body and each of said guard regions being in spaced relationship with said drain area and each of said guard regions abutting portions of said gate regions; said gate regions jointly with said guard regions being alternately positioned to surround said drain region; said source extending around said gate regions and said guard area; and a plurality of gate electrodes and each of said electrodes adherent to said surface and overlying corresponding gate regions and having each opposite end of each respective gate electrode extending at least to a corresponding portion of such guard region which abuts a respective gate region, and each of said electrodes including a gate oxide layer of substantially uniform thickness along its length positioned over a corresponding gate region, and spurious current flow between the two regions separated by said corresponding gate region is prevented by the combination of said guard region and said gate electrode and said guard region blocks current flow around said gate electrode, and said current flow through a respective gate region only flows under said gate electrode and a gate oxide layer of substantially uniform thickness along its length.
Claim 2
Dependent Claim
331 words
In a field effect transistor integrated circuit, the improvement comprising: a body of semiconductor material of a relatively high resistivity and first conductivity type and having an upper surface; a source region of relatively low resistivity and opposite conductivity type extending from said surface into said body; a drain region of relatively low resistivity and opposite conductivity type extending from said surface into said body, and said drain region being in spaced relationship with said source region; a plurality of gate regions positioned adjacent said drain region and between said drain region and said source region and each of said gate regions being of relatively high resistivity and first conductivity type and being fromed integrally with said body; a plurality of guard regions of said first type conductivity and lower resistivity when compared to said body extending from said surface into said body and each of said guard regions being in spaced relationship with said drain area and each of said guard regions abutting portions of said gate regions; said gate regions jointly with said guard regions being alternately positioned to surround said drain region; said source extending around said gate regions and said guard area; and a plurality of gate electrodes and each of said electrodes adherent to said surface and overlying corresponding gate regions and having each opposite end of each respective gate electrode extending at least to a corresponding portion of such guard region which abuts a respective gate region, and each of said electrodes including a gate oxide layer of substantially uniform thickness along its length positioned over a corresponding gate region, and spurious current flow between the two regions separated by said corresponding gate region is prevented by the combination of said guard region and said gate electrode and said guard region blocks current flow around said gate electrode, and said current flow through a respective gate region only flows under said gate electrode and a gate oxide layer of substantially uniform thickness along its length.
Claim 3
Dependent Claim
37 words
The field effect transistor of claim 1 in which each opposite end of each respective gate electrode is in registration with the corresponding portion of the guard region which abuts the gate region underlying the gate electrode.
Claim 4
Dependent Claim
35 words
The field effect transistor of claim 1 in which each opposite end of each respective gate electrode extends over the corresponding portion of the guard region which abuts the gate region underlying the gate electrode.
Claim 5
Dependent Claim
288 words
A field effect device comprising: a semiconductor body of relatively high resistivity and first conductivity type, and having at least an upper surface; source and drain regions of relatively low resistivity and opposite conductivity type extending from said surface into said body and said drain region being in spaced relationship with said source region, and said source region extending around said drain region; a plurality of gate regions positioned adjacent said drain region and between said drain region and said source region and each of said gate regions being of relatively high resistivity and first conductivity type and being formed integral with said body; a plurality of guard regions, and each of said guard regions being in spaced relationship with said drain region, and said guard areas abutting respective gate regions; said gate regions jointly with said guard regions being alternately positioned to surround said drain region; a plurality of gate electrodes and each of said gate electrodes adherent to said surface and overlying corresponding gate regions and having each of the opposite ends of each respective gate electrode extending along a portion of the length of said gate electrode at least to a corresponding portion of such guard region which abuts a respective gate region, and said gate electrode including a gate oxide layer of substantially uniform thickness along its length positioned over and in contact with respective gate regions; source of potential having a first potential level and a second potential level more negative than said first potential level; and means for electrically connecting one of said gate regions and said source region to said first level of potential for preventing signals from flowing from said source region to said drain region under said gate electrode.
Claim 6
Dependent Claim
288 words
A field effect device comprising: a semiconductor body of relatively high resistivity and first conductivity type, and having at least an upper surface; source and drain regions of relatively low resistivity and opposite conductivity type extending from said surface into said body and said drain region being in spaced relationship with said source region, and said source region extending around said drain region; a plurality of gate regions positioned adjacent said drain region and between said drain region and said source region and each of said gate regions being of relatively high resistivity and first conductivity type and being formed integral with said body; a plurality of guard regions, and each of said guard regions being in spaced relationship with said drain region, and said guard areas abutting respective gate regions; said gate regions jointly with said guard regions being alternately positioned to surround said drain region; a plurality of gate electrodes and each of said gate electrodes adherent to said surface and overlying corresponding gate regions and having each of the opposite ends of each respective gate electrode extending along a portion of the length of said gate electrode at least to a corresponding portion of such guard region which abuts a respective gate region, and said gate electrode including a gate oxide layer of substantially uniform thickness along its length positioned over and in contact with respective gate regions; source of potential having a first potential level and a second potential level more negative than said first potential level; and means for electrically connecting one of said gate regions and said source region to said first level of potential for preventing signals from flowing from said source region to said drain region under said gate electrode.
Claim 7
Dependent Claim
40 words
The field effect device of claim 4 in which the opposite ends of each respective gate electrode extend to and are in registration with a corresponding portion of the guard region which abuts the gate region underlying the gate electrode.
Claim 8
Dependent Claim
35 words
The field effect device of claim 4 in which the opposite ends of each respective gate electrode extend over a corresponding portion of the guard region which abuts the gate region underlying the gate electrode.
Claim 9
Dependent Claim
143 words
A field effect transistor comprising: a substrate of one conductivity type, spaced apart source and drain regions each of opposite conductivity type to said substrate, said source region extending around said drain region, at least one conductive gate electrode having two ends on an insulating layer over a space between said source and drain regions, at least one guard region of the same conductivity type as said substrate and having a higher dopant concentration than said substrate, the ends of said gate electrode extending at least to a corresponding portion of said at least one guard region, said at least one gate electrode and at least one guard region serving to isolate said source region from said drain region in the absence of a suitable potential applied to said gate electrode for allowing a current to flow between said source and drain regions.
Claim 10
Dependent Claim
143 words
A field effect transistor comprising: a substrate of one conductivity type, spaced apart source and drain regions each of opposite conductivity type to said substrate, said source region extending around said drain region, at least one conductive gate electrode having two ends on an insulating layer over a space between said source and drain regions, at least one guard region of the same conductivity type as said substrate and having a higher dopant concentration than said substrate, the ends of said gate electrode extending at least to a corresponding portion of said at least one guard region, said at least one gate electrode and at least one guard region serving to isolate said source region from said drain region in the absence of a suitable potential applied to said gate electrode for allowing a current to flow between said source and drain regions.
Claim 11
Dependent Claim
30 words
The field effect transistor of claim 7 in which the ends of said at least one gate electrode extend to a corresponding portion of said at least one guard region.
Claim 12
Dependent Claim
30 words
The field effect transistor of claim 7 in which the ends of said at least one gate electrode extend over a corresponding portion of said at least one guard region.
Claim 13
Dependent Claim
44 words
The field effect transistor of claim 7 having at least two gate electrodes and at least two guard regions, said gates and said guard regions being provided in an alternating arrangement around said drain region to isolate said drain region from said source region.
Claim 14
Dependent Claim
34 words
The field effect transistor of claim 7 including at least one consolidated region serving as the drain region of said field effect transistor and as a source region of a second field effect transistor.
Claim 15
Dependent Claim
14 words
An integrated circuit comprising a plurality of the field effect transistors of claim 7.
References Cited (Backward Citations)
US3440502A
Cited
US3518750A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-08-04 | 1979-02-03 | 1979-08-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-08-04 | 1983-02-03 | 1983-08-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-08-04 | 1987-02-03 | 1987-08-05 | $7700.00 | Window Closed / Lapsed |