Liquid crystal dynamic drive circuit

Claim 2

A display system comprising an information register for storing multi-digit information to be displayed, a plurality of liquid crystal display units each having a first optical state and a second optical state, said plurality of liquid crystal display units providing a visual indication of the multi-digit information at their first optical states, and means for applying to the liquid crystals signals of a high frequency sufficient to turn the liquid crystal units to their second optical states to erase said visual indication when said information is initially transmitted to the liquid crystal units.

Claim 3

A display system comprising an information register for storing multi-digit information to be displayed, a buffer register for accepting the information stored in the information register, a plurality of liquid crystal display units for displaying the multidigit information stored in the buffer register at their turbulence states, and means for applying to the liquid crystals signals of a high frequency sufficient to turn the liquid crystal units to their non-turbulence states only for the period of times where the information stored in the information register is introduced into the buffer register.

Claim 4

A display system comprising an information register for storing multi-digit information to be displayed, a buffer register for accepting the information stored in the information register, a plurality of liquid crystal display units for displaying the multidigit information stored in the buffer register at their turbulence states, and means for applying to the liquid crystals signals of a high frequency sufficient to turn the liquid crystal units to their non-turbulence states only for the period of times where the information stored in the information register is introduced into the buffer register.

Claim 5

A display system comprising an information register for storing multi-digit information to be displayed, a buffer register for accepting the information stored in the information register, a generator for generating a train of sequential timing signals, a plurality of liquid crystal display units for displaying the multidigit information stored in the buffer register at their turbulence states, each of the liquid crystal display units having a common electrode, a plurality of segment electrodes and a liquid crystal composition between the common and segment electrodes, a first selection circuit associated with the timing signal generator and the common electrodes of the liquid crystal units for selecting sequentially the common electrodes of the liquid crystal units in synchronization with the timing signals, a second selection circuit associated with the buffer register and the segment electrodes of the liquid crystal units for selecting the segment electrodes in accordance with the contents of the buffer register, and an additional circuit for applying across the common electrode and the segment electrodes of the liquid crystal units signals of a high frequency sufficient to turn the liquid crystal units to their non-turbulence states only for the period of time where the information stored in the information register is introduced into the buffer register.

Claim 6

A display system comprising an information register for storing multi-digit information to be displayed, a buffer register for accepting the information stored in the information register, a generator for generating a train of sequential timing signals, a plurality of liquid crystal display units for displaying the multidigit information stored in the buffer register at their turbulence states, each of the liquid crystal display units having a common electrode, a plurality of segment electrodes and a liquid crystal composition between the common and segment electrodes, a first selection circuit associated with the timing signal generator and the common electrodes of the liquid crystal units for selecting sequentially the common electrodes of the liquid crystal units in synchronization with the timing signals, a second selection circuit associated with the buffer register and the segment electrodes of the liquid crystal units for selecting the segment electrodes in accordance with the contents of the buffer register, and an additional circuit for applying across the common electrode and the segment electrodes of the liquid crystal units signals of a high frequency sufficient to turn the liquid crystal units to their non-turbulence states only for the period of time where the information stored in the information register is introduced into the buffer register.

Claim 7

A display system as defined in claim 3 wherein each signal to the common electrodes has a low frequency not capable of turning the liquid crystal unit to the non-turbulence state while each signal to the segment electrodes has the non-turbulence frequency.

Claim 8

A display system as defined in claim 4 whrein the common electrodes are held at an intermediate level of the levels of the information stored in the information register during the period where the information is intorduced into the buffer register.

Claim 9

A display system as defined in claim 3 wherein both the signals to the common electrode and the segment electrodes are of alternating voltage amplitude.

Claim 10

A display system as defined in claim 3 wherein the first and second selection circuits comprise amplitude converter circuits respectively.

Claim 11

A display system as defined in claim 7 wherein the amplitude converter circuit includes at least one pair of transistors capable of functioning as an emitter follower.

Claim 12

A display system for displaying multidigit information on a time-sharing basis through the use of a series of liquid crystal display units each having a common electrode and a plurality of segment electrodes and a liquid crystal composition between the common electrode and the segment electrodes, comprising: an information storage register storing multi-digit information to be displayed; a buffer circuit interposed between said information storage register and said common electrodes of said liquid crystal units for receiving the multi-digit information from said information storage register; means modifying the contents of said buffer circuit at a selected frequency sufficient to turn off said liquid crystal display units during the period of time wherein the information is transmitted from said information storage register to said buffer circuit; and erasing means synchronized with said buffer circuit and connected with said common electrodes of said liquid crystal unit during said information transmission periOd simultaneously biasing said common electrodes during said time period so that all said liquid crystal display units are turned off simultaneously at least during said time period when said information is transmitted from said storage register to said buffer circuit by said selected frequency of modification of the contents of said buffer register.

Claim 13

A display system for displaying multidigit information on a time-sharing basis through the use of a series of liquid crystal display units each having a common electrode and a plurality of segment electrodes and a liquid crystal composition between the common electrode and the segment electrodes, comprising: an information storage register storing multi-digit information to be displayed; a buffer circuit interposed between said information storage register and said common electrodes of said liquid crystal units for receiving the multi-digit information from said information storage register; means modifying the contents of said buffer circuit at a selected frequency sufficient to turn off said liquid crystal display units during the period of time wherein the information is transmitted from said information storage register to said buffer circuit; and erasing means synchronized with said buffer circuit and connected with said common electrodes of said liquid crystal unit during said information transmission periOd simultaneously biasing said common electrodes during said time period so that all said liquid crystal display units are turned off simultaneously at least during said time period when said information is transmitted from said storage register to said buffer circuit by said selected frequency of modification of the contents of said buffer register.