Analogue recursive process control system

Claim 2

A computational system comprising: a digital memory for storing a number of digital instruction words, each represented by a plurality of bits, said plurality of bits including a first group thereof for providing an analogue signal selection signal, a second group thereof for providing a function determining signal, and a third group thereof for providing a store selection signal, said digital memory having an input address line for each instruction word and an output line for each bit of the instruction word; control means for addressing one at a time said input lines of said memory for causing a selected oNe of said instruction words each to appear on the output lines for a short time period whose duration is determined by said control means; a plurality of inputs each for receiving a respective analogue input signal whose value is substantially constant during said short time period; input signal selection means connected to receive said first group of bits from said memory for selecting one of said input signals for said short time period; analogue computing means connected to receive said second group of bits and for producing an analogue output signal which is a selected analogue function of the selected input signal applied to a first input of said analogue computing means from said signal selection means, said computing means providing a substantially constant analogue output; a plurality of stores connected to receive the output of said analogue computing means for storing said output signal; store selection means connected to receive said third group of said bits for selecting one of said stores during the short time period such that the substantially constant analogue output of said computing means is applied to said selected store during said short time period; and at least one closed loop path from an output of one of said stores to one of said inputs.

Claim 3

A computational system as claimed in claim 1 further including a plurality of AND gates each having first and second inputs, each of the memory output lines for providing said second group of bits, also being connected to said first input of a corresponding AND gate, said output of each of said AND gates being connected to said control means, said computational system including a comparator selectively connectible through said store selection means to the output of said computing means for comparing said computing means output with a reference value, the output of said comparator being connected to said second input of each AND gate, whereby the outputs of said AND gates form a binary number in accordance with the output of said comparator, said control means being responsive to the outputs of said AND gates for providing an instruction word to said computing means corresponding to said binary number.

Claim 4

A computational system as claimed in claim 1 wherein said plurality of bits includes a fourth group of bits for providing a modifier bit control signal, said computing means comprises a variable gain amplifier circuit, said amplifier circuit comprising an operational amplifier, a negative feedback resistance connected thereto, an impedance ladder network connected to an input of said operational amplifier with transistor switches selectively controllable by said function determining signal from said digital memory to vary the transmissivity of said network, a buffer amplifier responsive to the output of said input signal selection means for providing an output to said impedance network, a phase-inverting amplifier connected to the output of said operational amplifier, and switch means selectively controllable by said modifier bit control signal from said digital memory to cause the output of said operational amplifier to bypass said phaseinverting amplifier.

Claim 5

A computational system as claimed in claim 1 wherein said plurality of bits includes a fourth group of bits for providing modifier bit control signals, said analogue computing means includes analogue mulitplier means including first and second inputs for multiplying two analogue values applied to said first and second inputs, said computational system also comprising first means for applying an output of onee of said stores representing one of said two analogue values at said first input of said multiplier means in response to a first modifier bit control signal from said digital memory, and second means for applying the content of another of said output stores representing the other of said two analogue values to said multiplier means in response to a second modifier bit control signal from said digital meMory.

Claim 6

A computational system as set forth in claim 4 further including switch means connected to an output line and responsive to a third modifier bit control signal for switching the output of said multiplier means through said store selection means to a selected store.

Claim 7

A computational system as claimed in claim 1, wherein said plurality of bits includes a fourth group thereof for providing modifier bit control signals, said analogue computing means comprising a second input terminal, said computational system further comprising a switch responsive to the modifier bit control signal derived from said digital memory for coupling the output of one of said stores to said second input terminal of said analogue computing means during a first short time period, said computing means further operative in response to said function determining signal to add during a second short time period the output of said one store to an input signal applied to said first input terminal from said switch selection means.

Claim 8

A computational system comprising: a digital memory for storing a number of digital instruction words, each represented by a plurality of bits, said plurality of bits including a first group thereof for providing an analogue signal selection signal, a second group thereof for providing a function determining signal, a third group thereof for providing a store selection signal, and a fourth group thereof for providing a modifier bit control signal, said digital memory having an input address line for each instruction word and an output line for each bit of the instruction word; control means for addressing one at a time said input lines of said digital memory for causing a selected one of said instruction words each to appear on the output lines for a short period whose duration is determined by said control means; a plurality of inputs, each for receiving a responsive analogue input signal whose value is substantially constant during said short time period; input signal selection means connected to receive said first group of bits from said memory for selecting one of said input signals for said short time period; analogue computing means connected to receive said second group of bits for producing an analogue output signal which is a selected analogue function of the selected input signal applied to a first input of said analogue computing means from said signal selection means, said analogue computing means providing a substantially constant analogue output, said analogue computing means including a variable gain amplifier circuit, said variable gain amplifier circuit comprising an operational amplifier, a negative feedback resistance connected thereto, an impedance ladder network connected to an input of said operational amplifier with transistor switdhes selectively controllable by said function determining signal from said digital memory to vary the transmissivity of said network, a buffer amplifier responsive to the output of said input signal selection means for providing an output to said impedance network, a phase-inverting amplifier connected to the output of said operational amplifier, and switch means selectively controllable by said modifier bit control signal from said digital memory to cause the output of said operational amplifier to bypass said phase-inverting amplifier.

Claim 9

A computational system comprising: a digital memory for storing a number of digital instruction words, each represented by a plurality of bits, said plurality of bits including a first group thereof for providing an analogue signal selection signal, a second group thereof for providing a function determining signal, a third group thereof for providing a store selection signal, and a fourth group thereof for providing a modifier bit control signal, said digital memory having an input address line for each instruction word and an output line for each bit of the instruction word; control means for addressing one at a time said input lines of said digital memory for causing a selected one of said instruction words each to appear on the output lines for a short period whose duration is determined by said control means; a plurality of inputs, each for receiving a responsive analogue input signal whose value is substantially constant during said short time period; input signal selection means connected to receive said first group of bits from said memory for selecting one of said input signals for said short time period; analogue computing means connected to receive said second group of bits for producing an analogue output signal which is a selected analogue function of the selected input signal applied to a first input of said analogue computing means from said signal selection means, said analogue computing means providing a substantially constant analogue output, said analogue computing means including a variable gain amplifier circuit, said variable gain amplifier circuit comprising an operational amplifier, a negative feedback resistance connected thereto, an impedance ladder network connected to an input of said operational amplifier with transistor switdhes selectively controllable by said function determining signal from said digital memory to vary the transmissivity of said network, a buffer amplifier responsive to the output of said input signal selection means for providing an output to said impedance network, a phase-inverting amplifier connected to the output of said operational amplifier, and switch means selectively controllable by said modifier bit control signal from said digital memory to cause the output of said operational amplifier to bypass said phase-inverting amplifier.