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Claim 2

A time delay device comprising a field-effect transistor having a semiconductor body comprising spaced source and drain regions of one type conductivity defining therebetween a channel region of said one type conductivity and a gate electrode for controlling the conduction level of the channel region, said gate electrode when pulsed establishing a depletion region in the channel reducing the conduction in the channel to a low level, and means for automatically increasing the conduction in the channel to a high level after a controlled time interval, said conduction increasing means including a rectifying junction within the body and means connected to the rectifying junction for at least temporarily biasing same in the forward direction, said biasing value being such that carriers injected by the forward baised junction cause contraction of the depletion region and increased channel conduction at a controlled rate producing the high level channel conduction at the end of the controlled time interval.

Claim 3

A time delay device as claimed in claim 1, wherein the value of said gate pulse is such that a depletion region is formed which extends substantially throughout the thickness of the channel region and which substantially electrically insulates the source region and the drain region from each other.

Claim 4

A time delay device as claimed in claim 2, wherein the distance between the rectifying junction and the depletion region is at most equal to the diffusion length of minority charge carriers in the channel region.

Claim 5

A time delay device as claimed in claim 1, wherein the rectifying junction belonging to the conduction increasing means is located in one of the source region and the drain region of the field-effect transistor, and the pulse applied to the gate electrode is such that a depletion region is formed in the channel region of the field-effect transistor and which extends throughout the thickness of the channel region and electrically insulates the source region and the drain region substantially entirely from each other whereby the said one region of the field-effect transistor containing the rectifying junction assumes an electrically floating potential.

Claim 6

A time delay device as claimed in claim 4, wherein the conduction increasing means comprises at least one further rectifying junction which is at least temporarily biased in the forward direction.

Claim 7

A time delay device as claimed in claim 1, wherein the field-effect transistor is an insulated gate field-effect transistor.

Claim 8

A time delay device as claimed in claim 1, wherein the semiconductor body has an epitaxial layer of one conductivity type which adjoins a surface of the semiconductor body and is provided on a semiconductor substrate of the opposite conductivity type, the source region and the drain region of the field-effect transistor being formed by regions of the epitaxial layer adjoining the said surface.

Claim 9

A time delay device as claimed in claim 7, wherein viewed in a direction transverse to the surface of the epitaxial layer, the gate electrode of the field-effect transistor has a closed shape, the part of the epitaxial layer which is surrounded by the gate electrode forming the drain region of the transistor, and at least a part of the epitaxial layer present outside the gate electrode forming the source region of the transistor.

Claim 10

A time delay device comprising a field-effect transistor having a semiconductor body comprising spaced source and drain regions of one type conductivity defining therebetween a channel region of said one type conductivity and a gate electrode for controlling the conduction level of the channel region, said transistor having low conduction and high conduction level states dependent upon the conduction level of its channel, source and drain terminals connected respectively to the source and drain regions, a utilization circuit connected to the source and drain terminals and including a source of potential and a load actuable upon the transistor reaching its high conduction level state, said gate electrode when voltage pulsed establishing a depletion region in the channel reducing the conduction in the channel to a low level, means for applying a voltage pulse to the gate electrode to establish a depletion region in the channel and set the transistor into its low conduction level state, and means for automatically increasing the conduction in the channel to a high level after a controlled time interval, said conduction increasing means including means furnishing free carriers causing contraction of the depletion region and increased channel conduction at a controlled rate producing the high conduction level state and actuation of the load at the end of the controlled time interval.

Claim 11

A time delay device comprising a field-effect transistor having a semiconductor body comprising spaced source and drain regions of one type conductivity defining therebetween a channel region of said one type conductivity and a gate electrode for controlling the conduction level of the channel region, said transistor having low conduction and high conduction level states dependent upon the conduction level of its channel, source and drain terminals connected respectively to the source and drain regions, a utilization circuit connected to the source and drain terminals and including a source of potential and a load actuable upon the transistor reaching its high conduction level state, said gate electrode when voltage pulsed establishing a depletion region in the channel reducing the conduction in the channel to a low level, means for applying a voltage pulse to the gate electrode to establish a depletion region in the channel and set the transistor into its low conduction level state, and means for automatically increasing the conduction in the channel to a high level after a controlled time interval, said conduction increasing means including means furnishing free carriers causing contraction of the depletion region and increased channel conduction at a controlled rate producing the high conduction level state and actuation of the load at the end of the controlled time interval.

Claim 12

A time delay device as claimed in claim 9, wherein the field-effect transistor is a junction field-effect transistor.

Claim 13

A time delay as claimed in claim 10, wherein the device comprises a first junction field-effect transistor having a source region and a drain region with an intermediately located channel region of a first conductivity type, the conduction increasing means comprising a rectifying junction located in one of the source region and drain region of the first transistor, and a second junction field-effect transistor having a source region, a drain region and an intermediately located channel region of one conductivity type, and a gate electrode which is conductivity connected to the gate electrode of the said first field-effect transistor.

Claim 14

A time delay device as claimed in claim 11, wherein the channel region of said first field-effect transistor has a smaller thickness than the channel region of said second field-effect transistors so that a depletion region can be formed in the channel region of said second field-effect transistor by applying a voltage to the gate electrodes of the field-effect transistors, said depletion region having a larger thickness than the depletion region which is formed in the channel region of said first field-effect transistor.

Claim 15

A time delay device as claimed in claim 12, wherein the semiconductor body comprises an epitaxial layer of one conductivity type on a substrate of the opposite conductivity type, the source and drain regions being located in the epitaxial layer, the substrate forms a common gate electrode for said two field-effect transistors, buried zones which have the same conductivity type as and a higher doping than the substrate are provided at the area of the interfaces between the substrate and the channel region of said first field-effect transistor and between the substrate and the channel region of said second field-effect transistor, the rectifying junction of the conduction increasing means being formed by a p-n junction between the epitaxial layer of one conductivity type and a surface zone of the opposite conductivity type provided in the epitaxial layer.

Claim 16

A time delay device as claimed in claim 13, wherein said second field-effect transistor comprises an insulated gate electrode which is provided on an insulating layer present on the surface of the epitaxial layer and separated from the epitaxial layer by said insulating layer and which, viewed in a direction transverse to the surface of the epitaxial layer, is present between the source region and the drain region of the said transistor.

Claim 17

A time delay device as claimed in claim 13, wherein at the area of the channel region of said first field-effect transistor an oxide layer is provided inset in the epitaxial layer from the surface of the epitaxial layer over at least a part of its thickness and, together with the oppositely located buried zone of the oppoSite conductivity type, defining the thickness of the channel region of said first field-effect transistor.