Abstract A standardized two-dimensional layout and method are disclosed for generating topologies for large scale integrated FET logic circuits for embodiment in a semiconductor wafer. The method is based upon the following steps. Dividing a photolithographic diffusion mask into an array of alternating parallel stripes denoting allowed and forbidden zones for diffusion. Defining the source and drain of an FET device by a juxtaposed pair of diffusion bar images on the mask, occupying two nearest neighbor allowed zones for diffusion, respectively. Referencing the location of the pair of diffusion bar images to the location on a second level, of the metallized gate for the device. Selecting the location of the metallized gate on the second level in accordance with gate wiring and overlap rules. Constraining the location of the metallized gate on the second level so that the referenced pair of diffusion bar images will fall within allowed zones for diffusion on the mask. A standardized layout of FET devices is thereby formed with 2* of freedom. A novel alternating series array of diffusion segments may be produced by the method, forming an AND logical function having a minimum transverse dimension when laid out.
Inventors
👤 George E Brechling
👤 John J Montren
Bibliographic Details
Application Number—
JurisdictionUS
Data Sourcegoogle_patents
Last Synchronized2026-10-28 13:02
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/90; H10D84/903
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
271 words
In an insulated gate field effect transistor integrated circuit logic function layout having a plurality of spaced parallel rows of diffusions of a first conductivity type in a semiconductor wafer of a second conductivity type with portions of said semiconductor wafer between adjacent diffusions defining input channel regions sof field offset transistor devices, selected ones of said parallel diffusion being segmented into reduced lengths, wherein the improvement comprises: a first and third diffusion segment in a first row, said first diffusion segment operating as a source diffusion in a first field effect transistor, said third diffusion segment operating as a drain diffusion in a second field effect transistor, a second diffusion segment in a second row adjacent to said first row, said second diffusion segment operating as a drAin diffusion in said first field effect transistor and as a source diffusion in said second field effect transistor, each of said diffusion segments in said first row being partially juxtaposed with each of the nearest diffusion segments in said second row so as to define a sequence of channel regions bounded by an alternating sequence of diffusion segments, at least one gate electrode formed over the channel region defined by each juxtaposed pair of diffusion segments, said first and second diffusion segments forming said first field effect transistor whose drain diffusion is series connected by means of said second diffusion to the source diffusion of said second field effect transistor which is formed by said second and said third diffusion segments, whereby a logical function is formed in a two dimensional, alternating series array, providing a high logic power per unit area.
Claim 2
Dependent Claim
271 words
In an insulated gate field effect transistor integrated circuit logic function layout having a plurality of spaced parallel rows of diffusions of a first conductivity type in a semiconductor wafer of a second conductivity type with portions of said semiconductor wafer between adjacent diffusions defining input channel regions sof field offset transistor devices, selected ones of said parallel diffusion being segmented into reduced lengths, wherein the improvement comprises: a first and third diffusion segment in a first row, said first diffusion segment operating as a source diffusion in a first field effect transistor, said third diffusion segment operating as a drain diffusion in a second field effect transistor, a second diffusion segment in a second row adjacent to said first row, said second diffusion segment operating as a drAin diffusion in said first field effect transistor and as a source diffusion in said second field effect transistor, each of said diffusion segments in said first row being partially juxtaposed with each of the nearest diffusion segments in said second row so as to define a sequence of channel regions bounded by an alternating sequence of diffusion segments, at least one gate electrode formed over the channel region defined by each juxtaposed pair of diffusion segments, said first and second diffusion segments forming said first field effect transistor whose drain diffusion is series connected by means of said second diffusion to the source diffusion of said second field effect transistor which is formed by said second and said third diffusion segments, whereby a logical function is formed in a two dimensional, alternating series array, providing a high logic power per unit area.