US3896477A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Multilayer semiconductor switching devices
Assignee: Individual
•
Filing: 1973-11-07
•
Granted: 1975-07-22
•
Expires: 1993-11-07
Abstract
Abstract The specification discloses a semiconductor device including at least three layers of one and the opposite conductivity type of semiconductor material interleaved with one another to form P-N junctions within the body. A plurality of discrete regions of one conductivity type are formed in each of the exterior layers of the other conductivity type and extend normally from the external surfaces into the interiors of each of the exterior layers. The discrete regions are closely spaced apart throughout the surface of the exterior layers and the discrete regions in one layer are aligned with the discrete regions in the other layer to cause voltage drops adjacent the discrete regions which are normal to the P-N junctions during initial conduction of the device. First and second spaced apart electrodes are connected in low resistance ohmic contact with the discrete regions and one of the exterior layers. A third electrode is connected to the other of the exterior layers of the other conductivity type.
Inventors
- 👤 Jearld L Hutson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 11:52
CPC Classifications
H; H10; H10W; H10W72/00; H10D; H10D99/00
Claims Analysis
Total Claims: 33
Claim 1
Independent Claim
226 words
A semiconductor device comprising: a body of semiconductor material having at least three layers including an internal layer of one conductivity type bounded on opposite sides by two layers of the opposite conductivity type to form a plurality of P-N junctions, said body having first and second opposed outer surfaces of said opposite conductivity type, an array of discrete regions of said one conductivity type spaced apart over said first and second outer surfaces of said body; the cross sections of said discrete regions parallel to said outer surfaces being symmetrical and said discrete regions extending inwardly from said first and second outer surfaces into the interior of said layers of opposite conductivity type, each of said discrete regions in said first outer surface being vertically aligned with a discrete region in said second outer surface, in order to substantially eliminate lateral current flow in said device during conduction upon the application of predetermined bias potential, a first electrode in low resistance ohmic contact with the exposed surfaces of a plurality of said discrete regions and with a portion of said first outer surface, a second electrode connected to a source of control bias and connected to said first outer surface and contacting a pLurality of said discrete regions and spaced apart from said first electrode, and a third electrode connected to said second outer surface.
Claim 2
Dependent Claim
226 words
A semiconductor device comprising: a body of semiconductor material having at least three layers including an internal layer of one conductivity type bounded on opposite sides by two layers of the opposite conductivity type to form a plurality of P-N junctions, said body having first and second opposed outer surfaces of said opposite conductivity type, an array of discrete regions of said one conductivity type spaced apart over said first and second outer surfaces of said body; the cross sections of said discrete regions parallel to said outer surfaces being symmetrical and said discrete regions extending inwardly from said first and second outer surfaces into the interior of said layers of opposite conductivity type, each of said discrete regions in said first outer surface being vertically aligned with a discrete region in said second outer surface, in order to substantially eliminate lateral current flow in said device during conduction upon the application of predetermined bias potential, a first electrode in low resistance ohmic contact with the exposed surfaces of a plurality of said discrete regions and with a portion of said first outer surface, a second electrode connected to a source of control bias and connected to said first outer surface and contacting a pLurality of said discrete regions and spaced apart from said first electrode, and a third electrode connected to said second outer surface.
Claim 3
Dependent Claim
33 words
The semiconductor device of claim 1 wherein the entire surface area of said layers of opposite conductivity type conducts during triggering of said device when predetermined bias potential is applied to said electrodes.
Claim 4
Dependent Claim
36 words
The semiconductor device of claim 1 wherein a voltage drop occurs adjacent said regions which is normal to said outer surfaces during conduction of said device after a predetermined bias potential is applied to said electrodes.
Claim 5
Dependent Claim
59 words
The semiconductor device of claim 1 and further comprising a layer of highly doped semiconductor material of said opposite conductivity type formed over said first and second outer surfaces of said body and extending between said discrete regions to provide isolation thereto, the thickness of said highly doped semiconductor material being less than the thickness of said three layers.
Claim 6
Dependent Claim
52 words
The semiconductor device of claim 1 wherein the cross sectional areas of said regions parallel to said surfaces are generally rectangular and said regions are spaced apart over the entire area of said first and second outer surface, with intervals of opposite conductivity type disposed between and surrounding each of said regions.
Claim 7
Dependent Claim
39 words
A semiconductor device of claim 1 wherein said regions are elongated and have their lengths disposed normal to said outer surfaces, and wherein said regions are spaced about the outer surfaces of the body in a predetermined symmetrical array.
Claim 8
Dependent Claim
18 words
The semiconductor device of claim 1 and further comprising a groove disposed between said first and second electrodes.
Claim 9
Dependent Claim
23 words
The semiconductor device of claim 1 and further comprising a fourth electrode spaced apart from said third electrode on said second outer surface.
Claim 10
Dependent Claim
15 words
The semiconductor device of claim 1 wherein said regions are comprised of N-type conductivity material.
Claim 11
Dependent Claim
28 words
The semiconductor device of claim 9 and further comprising a layer of P+ semiconductor material disposed over said first and second outer surfaces and surrounding said discrete regions.
Claim 12
Dependent Claim
181 words
A semiconductor device comprising: a body including three layers of alternating opposite conductivity types of semiconductor material, a layer of one conductivity type being disposed between exterior layers of the other conductivity type to form two P-N junctions within said body, an array of discrete regions of said one conductivity type formed in both of said exterior layers and extending normally from the external surfaces into the interiors of said exterior layers, said discrete regions being spaced apart throughout said exterior layers and regions in one exterior layer being directly vertically aligned with regions in the other exterior layer to cause a voltage drop adjacent said regions normal to said P-N junctions during initial conduction of said device upon the application of a predetermined bias potential, first and second spaced apart electrodes connected in low resistance ohmic contact each with a plurality of said discrete regions and one of said exterior layers, a source of control bias connected to said second electrode, and at least a third electrode connected to the other of said exterior layers of the other conductivity type.
Claim 13
Dependent Claim
181 words
A semiconductor device comprising: a body including three layers of alternating opposite conductivity types of semiconductor material, a layer of one conductivity type being disposed between exterior layers of the other conductivity type to form two P-N junctions within said body, an array of discrete regions of said one conductivity type formed in both of said exterior layers and extending normally from the external surfaces into the interiors of said exterior layers, said discrete regions being spaced apart throughout said exterior layers and regions in one exterior layer being directly vertically aligned with regions in the other exterior layer to cause a voltage drop adjacent said regions normal to said P-N junctions during initial conduction of said device upon the application of a predetermined bias potential, first and second spaced apart electrodes connected in low resistance ohmic contact each with a plurality of said discrete regions and one of said exterior layers, a source of control bias connected to said second electrode, and at least a third electrode connected to the other of said exterior layers of the other conductivity type.
Claim 14
Dependent Claim
44 words
The semiconductor device of claim 11 wherein said discrete regions are elongated and wherein each discrete region in one of said exterior layers is aligned along its longitudinal axis with the longitudinal axis of a discrete region in the other of said exterior layers.
Claim 15
Dependent Claim
20 words
The semiconductor device of claim 12 wherein the entire surface of said exterior layers conducts during triggering of said device.
Claim 16
Dependent Claim
42 words
The semiconductor device of claim 11 and further comprising a thin layer of semiconductor material of said other conductivity type having a higher resistivity than said discrete regions disposed over said external surface of said exteRior layers and surrounding said discrete regions.
Claim 17
Dependent Claim
17 words
The semiconductor device of claim 14 wherein said thin layer of semiconductor material comprises P+ type material.
Claim 18
Dependent Claim
40 words
The semiconductor device of claim 11 wherein said discrete regions are separated from one another by thin intervals of said other conductivity type and wherein said first and second electrodes are spaced apart by at least one of said intervals.
Claim 19
Dependent Claim
41 words
The semiconductor device of claim 11 wherein the cross sections of said regions are generally square and have a thickness of less than 10 mils, the lengths of said regions being directed normal to said external surfaces of said exterior layers.
Claim 20
Dependent Claim
21 words
The semiconductor device of claim 11 and further comprising a groove in said exterior layer separating said first and second electrodes.
Claim 21
Dependent Claim
22 words
The semiconductor device of claim 18 and further comprising a groove surrounding a central area on said other of said exterior layers.
Claim 22
Dependent Claim
25 words
A semiconductor device of claim 11 and further comprising a fourth electrode spaced apart from said third electrode on said other of said exterior layers.
Claim 23
Dependent Claim
195 words
A semiconductor device comprising: a body of semiconductor material including a plurality of interleaved layers of opposite semiconductor material type to form a plurality of P-N junctions, an array of substantially identical discrete regions of semiconductor material of one conductivity type formed in two opposite exterior layers each of the opposite conductivity type, said regions having generally symmetrical cross sections with thicknesses less than 25 mils, said discrete regions extending from the external surfaces normally into the interiors of said layers, said regions being closely spaced apart over the surface areas of said exterior layers with intervals of said opposite conductivity type disposed between and surrounding said regions, the axes of said discrete regions in one of said exterior layers being aligned with the axes of said discrete regions in the other of said exterior layers, first and second electrodes contacting one of said exterior surfaces and each contacting a plurality of said regions and spaced apart by at least one of said intervals of said opposite conductivity type, a source of control bias connected to said second electrode, and a third electrode connected to the other exterior layer of semiconductor material of said body.
Claim 24
Dependent Claim
195 words
A semiconductor device comprising: a body of semiconductor material including a plurality of interleaved layers of opposite semiconductor material type to form a plurality of P-N junctions, an array of substantially identical discrete regions of semiconductor material of one conductivity type formed in two opposite exterior layers each of the opposite conductivity type, said regions having generally symmetrical cross sections with thicknesses less than 25 mils, said discrete regions extending from the external surfaces normally into the interiors of said layers, said regions being closely spaced apart over the surface areas of said exterior layers with intervals of said opposite conductivity type disposed between and surrounding said regions, the axes of said discrete regions in one of said exterior layers being aligned with the axes of said discrete regions in the other of said exterior layers, first and second electrodes contacting one of said exterior surfaces and each contacting a plurality of said regions and spaced apart by at least one of said intervals of said opposite conductivity type, a source of control bias connected to said second electrode, and a third electrode connected to the other exterior layer of semiconductor material of said body.
Claim 25
Dependent Claim
38 words
The semiconductor device of claim 21 and further comprising a thin layer of semiconductor material of said opposite conductivity type having a higher resistivity than said discrete regions disposed over said external surface and surrounding said discrete regions.
Claim 26
Dependent Claim
16 words
The semiconductor device of claim 21 wherein said thin layer of semiconductor material comprises P+ material.
Claim 27
Dependent Claim
40 words
The semiconductor device of claim 21 wherein a voltage drop occurs along the lengths of said regions which is parallel to the longitudinal axes of said regions during initial conduction of said devices upon application of a predetermined bias potential.
Claim 28
Dependent Claim
17 words
The semiconductor device of claim 21 and further comprising a groove separating said first and second electrodes.
Claim 29
Dependent Claim
25 words
The semiconductor device of claim 21 wherein said first and second electrodes are spaced apart by at least one interval of said other conductivity type.
Claim 30
Dependent Claim
18 words
The semiconductor device of claim 21 and further comprising a fourth electrode spaced apart from said third electrode.
Claim 31
Dependent Claim
48 words
The semiconductor device of claim 21 wherein said first electrode is disposed in the center of said exterior surface and is separated by said second electrode by a groove, and a groove formed in said other exterior layer to define a center area aligned with said first electrode.
Claim 32
Dependent Claim
15 words
The semiconductor device of claim 28 wherein said center area comprises said one conductivity type.
Claim 33
Dependent Claim
14 words
The semiconductor device of claim 29 wherein said grooves are filled with passivating material.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-07-21 | 1979-01-20 | 1979-07-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-07-21 | 1983-01-20 | 1983-07-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-07-21 | 1987-01-20 | 1987-07-22 | $7700.00 | Window Closed / Lapsed |