Synchronous drive system for a d.c. motor

Claim 2

A drive system for a D.C. motor comprising: reference signal generating means having a predetermined frequency, motor speed detecting means for generating a signal of frequency corresponding to rotational speed of the D.C. motor, synchronous drive controlling means for the motor, said controlling means being disposed so as to receive signals from said reference signal generating means and signals from said motor speed detecting means and generating driving signals for the motor corresponding to the phase difference between both said signals, delaying means connected to said reference signal generating means to delay said reference signal for a predetermined time, and adjusting means capable of being connected to said delaying means and said synchronous drive controlling means and comparing input signals from both said means so as to adjust the output of said synchronous drive controlling means, said adjusting means controlling duty of driving current for the D.C. motor to the value close to approximately 100%.

Claim 3

The drive system according to claim 1 in which said output adjusting means includes a circuit for delaying phase of said reference signal to a predetermined value not greater than one period of said reference signal.

Claim 4

The drive system according to claim 1 in which said output adjusting means further includes a circuit for delaying phase of said reference signal to a predetermined value, a first D-A converter connected to said delaying circuit, a second D-A converter connected to said synchronous drive controlling means to convert a signal from said means into an analog amount, and a comparing circuit connected to said first and second D-A converters to compare both analog signals therefrom and to generate controlling signals to set duty of the D.C. motor to the value close to approximately 100%.

Claim 5

The drive system according to claim 1 in which said output adjusting means further includes a transistor circuit for regulating input voltage from said synchronous drive controlling means.

Claim 6

The drive system according to claim 1 in which said motor synchronous drive controlling means includes a flip-flop circuit set by the reference signaL from said reference signal generating means and reset by the signal from said motor speed detecting means.

Claim 7

The drive system according to claim 1 in which said synchronous drive controlling means includes D.C. motor reversion switching means.

Claim 8

A drive system for a D.C. motor comprising: reference signal generating means having a predetermined frequency to synchronize a D.C. motor, motor speed detecting means for generating a signal of frequency corresponding to rotational speed of the D.C. motor, first control signal generating means for generating motor synchronous driving signals, said first control signal generating means generating signals according to the first signal system for synchronously driving the D.C. motor in response to the signal from said reference signal generating means and the signal from said speed detecting means, and second control signal generating means for controlling duty of the D.C. motor, said second means being so related as to apply output to the final stage of said first control means and to generate controlling signals to set duty of driving current of the D.C. motor to the value close to approximately 100%.

Claim 9

A drive system for a D.C. motor comprising: reference signal generating means having a predetermined frequency to synchronize a D.C. motor, motor speed detecting means for generating a signal of frequency corresponding to rotational speed of the D.C. motor, first control signal generating means for generating motor synchronous driving signals, said first control signal generating means generating signals according to the first signal system for synchronously driving the D.C. motor in response to the signal from said reference signal generating means and the signal from said speed detecting means, and second control signal generating means for controlling duty of the D.C. motor, said second means being so related as to apply output to the final stage of said first control means and to generate controlling signals to set duty of driving current of the D.C. motor to the value close to approximately 100%.

Claim 10

The drive system according to claim 7 in which said second control signal generating means includes delaying means for delaying phase of said reference signal by a predetermined time lag in order to form the reference signal so as to set said duty to the value close to approximately 100%.

Claim 11

The drive system according to claim 7 in which said first control signal generating means includes means for amplifying signals for driving the D.C. motor in the final stage of the signal system in said first controlling means.

Claim 12

The drive system according to claim 9 in which said second control signal generating means includes means connected to the input side of said amplifying means to adjust the level of voltage applied to said amplifying means from the power source.

Claim 13

The drive system according to claim 9 in which said amplifying means includes a bridge connection type transistor circuit.

Claim 14

A drive system for a D.C. motor comprising: reference signal generating means having a predetermined frequency to synchronize a D.C. motor, motor speed detecting means for generating a signal of frequency corresponding to rotational speed of the D.C. motor, D.C. motor drive controlling means for generating a D.C. motor energizing signal in response to the input of said reference signal and an interrupting signal of D.C. motor energizing in response to the signal input from said motor speed detecting means so as to synchronize with the frequency of said reference signal, and D.C. motor braking signal generating means with a phase corresponding to the signal from said motor speed detecting means, said braking signal generating means being connected to the motor so as to feed the braking signal held for a predetermined time to the D.C. motor when energization for driving the D.C. motor is interrupted, whereby said motor may overcome the braking action and duration of energization at the time of drive may be prolonged to increase duty.

Claim 15

A drive system for a D.C. motor comprising: reference signal generating means having a predetermined frequency to synchronize a D.C. motor, motor speed detecting means for generating a signal of frequency corresponding to rotational speed of the D.C. motor, D.C. motor drive controlling means for generating a D.C. motor energizing signal in response to the input of said reference signal and an interrupting signal of D.C. motor energizing in response to the signal input from said motor speed detecting means so as to synchronize with the frequency of said reference signal, and D.C. motor braking signal generating means with a phase corresponding to the signal from said motor speed detecting means, said braking signal generating means being connected to the motor so as to feed the braking signal held for a predetermined time to the D.C. motor when energization for driving the D.C. motor is interrupted, whereby said motor may overcome the braking action and duration of energization at the time of drive may be prolonged to increase duty.

Claim 16

The drive system according to claim 12 in which said braking signal generating means includes a monostable multivibrator driven into operative condicion with a phase in response to the output signal from said motor speed detecting means.

Claim 17

The drive system according to claim 12 in which said D.C. motor drive controlling means includes a flip-flop circuit, said circuit being set in response to the input of said reference signal and reset in response to the signal input from said motor speed detecting means, signal switching means, said switching means reversing output channels of the output signal from said flip-flop circuit and the output signal from said braking signal generating means, and symmetrical amplifying means, said amplifying means being connected to output side of said sigNal switching means to reverse the driving direction of D.C. motor in response to the reversion of output signal thereof.

Claim 18

The drive system according to claim 14 in which said symmetrical amplifying means includes a bridge type transistor circuit.

Claim 19

A drive system for a D.C. motor comprising: reference signal generating means having a predetermined frequency to synchronize a D.C. motor, motor speed detecting means for generating a signal of frequency corresponding to rotational speed of the D.C. motor, a flip-flop circuit set in response to the input of said reference signal and reset in response to the input of the output signal from said motor speed detecting means. a bridge type transistor circuit for amplifying output from said flip-flop circuit, a delaying circuit connected to said reference signal generating means to delay the phase of said reference signal for a fixed time within a period of said signal, a comparing circuit for comparing a signal corresponding to output from said flip-flop circuit with a signal corresponding to output from said delaying circuit to thereby generate a signal corresponding to the difference therebetween, and an adjusting circuit connected to said comparing circuit and said transistor circuit to adjust the voltage level of power source applied to said transistor circuit in response to output of said comparing circuit, whereby duty of driving current supplied to the D.C. motor from said transistor circuit may be increased.

Claim 20

A drive system for a D.C. motor comprising: reference signal generating means having a predetermined frequency to synchronize a D.C. motor, motor speed detecting means for generating a signal of frequency corresponding to rotational speed of the D.C. motor, a flip-flop circuit set in response to the input of said reference signal and reset in response to the input of the output signal from said motor speed detecting means. a bridge type transistor circuit for amplifying output from said flip-flop circuit, a delaying circuit connected to said reference signal generating means to delay the phase of said reference signal for a fixed time within a period of said signal, a comparing circuit for comparing a signal corresponding to output from said flip-flop circuit with a signal corresponding to output from said delaying circuit to thereby generate a signal corresponding to the difference therebetween, and an adjusting circuit connected to said comparing circuit and said transistor circuit to adjust the voltage level of power source applied to said transistor circuit in response to output of said comparing circuit, whereby duty of driving current supplied to the D.C. motor from said transistor circuit may be increased.