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US3895360A
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Block oriented random access memory
Assignee: Westinghouse Electric Corp
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Filing: 1974-01-29
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Granted: 1975-07-15
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Expires: 1994-01-29
Abstract
Abstract A block oriented random access memory (BORAM) is disclosed as comprising a plurality of memory arrays of metal-nitride-oxide semiconductor (MNOS) memory elements. Each memory array includes a plurality of the MNOS memory elements disposed in rows and columns, and serial or sequential means such as a shift register for writing and reading data to and from the memory elements through column conductors associated with each column of the memory elements. A temporary storage means such as a latch is inserted between each stage of the shift register and the column conductor, whereby a multiplexing function can be performed between the stage outputs of the shift register and the columns of the memory elements. Address means is provided for the rows of memory elements, whereby a row may be selected for entry of data through its associated column conductor. In one illustrative embodiment, a plurality of such assemblies is assembled into a block capable of being separately addressed, wherein each such assembly is capable of storing one bit of a multi-bit word of data. In turn, a plurality of such blocks is assembled to form the block oriented random access memory, wherein each such block may be randomly accessed, and the data therein sequentially read and written.
Inventors
- 👤 James Ronald Cricchi
- 👤 Franklyn C Blaha
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 19:26
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0466; G11C8/00; G11C8/04
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
297 words
A memory system for storing an input signal comprising a plurality of bits comprising: a. a matrix of memory elements disposed in a matrix of rows and columns, each of said memory elements capable of being disposed to at least first and second states corresponding to the input signal; b. address means responsive to an address signal designating at least one of the matrix rows, for actuating the designated row of said memory matrix to facilitate reading and writing of data onto the memory elements of the designated row; c. sequential storage means comprising a plurality of stages, each stage corresponding to a column of said memory matrix, said sequential storage means disposed to receive the input signal iN a sequential fashion and for storing a portion of the input signal in each of said stages, said sequential storage means upon the completion of the entry of the portions of the input signal in a given number of its stages effecting a transfer of the signal portions along corresponding columns of said memory matrix, whereby the portions of the input signal are written onto said memory elements of the addressed row; and d. intermediate storage and detection means interconnected between said sequential storage means and said memory matrix for temporarily storing the portions of the input signal, and for detecting whether said memory elements of the designated row are in their first and second stages and for providing corresponding first and second outputs to said corresponding stages of said shift register, after entry of the outputs from said memory matrix said sequential storage means sequentially transferring the outputs from said sequential storage means to provide a composite output comprised of the first and second outputs as derived in parallel from said memory elements of said matrix columns.
Claim 2
Dependent Claim
297 words
A memory system for storing an input signal comprising a plurality of bits comprising: a. a matrix of memory elements disposed in a matrix of rows and columns, each of said memory elements capable of being disposed to at least first and second states corresponding to the input signal; b. address means responsive to an address signal designating at least one of the matrix rows, for actuating the designated row of said memory matrix to facilitate reading and writing of data onto the memory elements of the designated row; c. sequential storage means comprising a plurality of stages, each stage corresponding to a column of said memory matrix, said sequential storage means disposed to receive the input signal iN a sequential fashion and for storing a portion of the input signal in each of said stages, said sequential storage means upon the completion of the entry of the portions of the input signal in a given number of its stages effecting a transfer of the signal portions along corresponding columns of said memory matrix, whereby the portions of the input signal are written onto said memory elements of the addressed row; and d. intermediate storage and detection means interconnected between said sequential storage means and said memory matrix for temporarily storing the portions of the input signal, and for detecting whether said memory elements of the designated row are in their first and second stages and for providing corresponding first and second outputs to said corresponding stages of said shift register, after entry of the outputs from said memory matrix said sequential storage means sequentially transferring the outputs from said sequential storage means to provide a composite output comprised of the first and second outputs as derived in parallel from said memory elements of said matrix columns.
Claim 3
Dependent Claim
89 words
A block oriented memory system comprising a plurality of memory blocks for writing the input signal in binary form and reading out data words comprising a selected number of bits, each of said blocks comprising a plurality of the memory systems as claimed in claim 1, one for each bit of the data, each of said memory blocks responsive to a unique block signal whereby the bits of the data words are written in and read out in parallel to and from corresponding memory systems of that memory block.
Claim 4
Dependent Claim
20 words
The memory system as claimed in claim 1, wherein each of said memory elements comprises an MNOS field effect transistor.
Claim 5
Dependent Claim
43 words
The memory system as claimed in claim 2, wherein each of said MNOS field effect transistors comprises a drain, a source and a gate terminal and is disposed on a common semiconductive substrate with the other MNOS field effect transistors of said matrix.
Claim 6
Dependent Claim
30 words
The memory system as claimed in claim 4, wherein each of said MNOS field effect transistors includes a fourth terminal connected to said substrate of said MNOS field effect transistor.
Claim 7
Dependent Claim
47 words
The memory system as claimed in claim 5, wherein there is included means for applying a CL signal to each of said fourth terminals of said MNOS field effect transistors of said matrix, whereby each of said MNOS field effect transistors is disposed to its first state.
Claim 8
Dependent Claim
60 words
The memory system as claimed in claim 1, wherein there is further included means for writing associated with said address means for applying a write biasing signal to the actuated row of said memory matrix to effect the writing of the input signal as applied by said intermediate storage and detection means to said memory elements of said designated row.
Claim 9
Dependent Claim
121 words
The memory system as claimed in claim 1, wherein said intermediate storage and detection means comprises a plurality of bistable circuits, each coupled to a corresponding column of said matrix and comprising first and second switches, each of said first and second switches comprising a first, control terminal for determining the impedance presented between its second and third terminals, said first terminal of said second switch being coupled to a first, detection node connected with said second terminal of said first switch and with its corresponding column of said matrix, said first electrode of said first switch being coupled to a second node connected with said second terminal of said second switch and further, providing the output of said bistable circuit.
Claim 10
Dependent Claim
21 words
The memory system as claimed in claim 8, wherein said first and second switches each comprise an MNOS field effect transistor.
Claim 11
Dependent Claim
148 words
The memory system as claimed in claim 8, wherein each of said bistable circuits comprises first biasing means for applying a first biasing voltage to said second node, of a magnitude selected such that if said one memory element coupled by said column to said first node is in itS first state, said second switch is rendered conductive to apply a second biasing voltage to said first electrode of said first switch disposing said first switch to its non-conductive state and providing a first output signal indicative of the first state of said memory element, and that if said one memory element is in its second state, said first switch is rendered conductive first thereby applying said second biasing voltage to said first electrode of said second switch to render said second switch non-conductive and providing the second biasing voltage as the second output of said bistable circuit.
Claim 12
Dependent Claim
80 words
The memory system as claimed in claim 10, wherein said bistable circuit further comprises switch means interconnected between each of said first electrodes of said first and second switches and the second biasing voltage, and address enable means for developing and applying an address enable signal to said switch means to render said switch means non-conductive after the application of the address signal to said address means, whereby said bistable circuit may respond to the outputs of said memory elements.
Claim 13
Dependent Claim
101 words
The memory system as claimed in claim 10, wherein each of said memory elements comprises an MNOS transistor capable of being disposed to a high threshold and a low threshold state, and comprising source, drain and gate electrodes, said address means comprising means for applying a read-bias voltage to said designated row of a suitable voltage such that said sources of said MNOS field effect transistors disposed in their low state will dispose said bistable circuit to provide its first output and said MNOS field effect transistors in their high state will dispose said bistable circuit to provide its second output.
Claim 14
Dependent Claim
69 words
The memory system as claimed in claim 12, wherein the read-bias voltage established upon the gate electrodes of said MNOS field effect transistors and the voltage to which the MNOS field effect transistors and the voltage to which the sources of said aforementioned MNOS field effect transistors charge in their high state, re-write the input signals into said MNOS field effect transistors devices upon each read-out of data therefrom.
Claim 15
Dependent Claim
105 words
The memory system as claimed in claim 1, wherein there is included means for developing an address enable signal, and first and second clamping means associated respectively with said columns and rows of said matrix for selectively applying first and second biasing voltages to said columns and rows of said matrix, respectively, said address enable means applying the address enable signal to each of said first and second clamping means after the application of the address signals to said address means to render said first and second clamping means non-conductive and to disconnnect said rows and conductors from the first and second biasing voltages, respectively.
Claim 16
Dependent Claim
53 words
The memory system as claimed in claim 14, wherein there is further included address buffer means for receiving and storing the address signal, said address means responsive to the address signal as stored in said address buffer means for actuating the designated row of said memory matrix in accordance with the address signal.
Claim 17
Dependent Claim
55 words
The memory system as claimed in claim 15, wherein there is included transfer means for effecting transfer of the input signals from said sequential storage means through said intermediate storage and detection means to said columns of said memory matrix after the application of the address enable signals to said first and second clamping means.
Claim 18
Dependent Claim
84 words
The memory system as claimed in claim 16, wherein there is further included write means for applying a WRITE signal after the transfer of the input signals to said columns of said matrix, to said address buffer means to effect transfer of the address signals to said address means, whereby the designated row is actuated and said memory elements are disposed to one of their first and second states in accordance with the input signals transferred thereto Along said columns of said memory matrix.
References Cited (Backward Citations)
US3742460A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-07-14 | 1979-01-13 | 1979-07-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-07-14 | 1983-01-13 | 1983-07-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-07-14 | 1987-01-13 | 1987-07-15 | $7700.00 | Window Closed / Lapsed |