Method and system for furnishing an indication of the deviation of the actual frequency of a low frequency signal from a nominal frequency

Claim 2

Method for furnishing an eror signal indicative of deviation of the actual frequency of a test signal from a nominal frequency, comprising, in combination, steps of furnishing a high-frequency signal having a frequency substantially exceeding said nominal frequency, counting the cycles of saiD high-frequency signal by sequential frequency divisions in such a manner that a first counting signal is created, said first counting signal comprising a first pulse sequence having a frequency substantially less than said frequency of said high-frequency signal but exceeding said nominal frequency, simultaneously counting said cycles of said high-frequency signal by frequency division in such a manner that a second counting signal is created, said second counting signal comprising a second pulse sequence having a frequency corresponding to the frequency of said first pulse sequence; re-starting said counting to create said first counting signal at predetermined time instants in selected cycles of said test signal, thereby creating phase shift between said first and second pulse sequence; and measuring said phase shift, the so measured phase shift constituting said error signal.

Claim 3

A method as set forth in claim 1, wherein said selected cycles of said test signal are alternate cycles, and said counting for creating said second counting signal is re-started at corresponding predetermined time instants of the remaining ones of said cycles of said test signal.

Claim 4

A method as set forth in claim 2, wherein said step of measuring said phase difference comprises combining said first and second pulse sequence in such a manner that a resultant pulse sequence is formed, said resultant pulse sequence having a pulse only in the simultaneous presence of a pulse of said first pulse sequence and absence of a pulse of said second pulse sequence.

Claim 5

A method as set forth in claim 2, wherein the frequency of said first and second pulse sequence is a determined harmonic of said nominal frequency of said test signal.

Claim 6

A method as set forth in claim 2, further comprising the step of counting said cycles of said high-frequency signal, thereby creating a third counting signal corresponding to the number of so counted cycles, said third counting signal comprising a third pulse sequence having a frequency corresponding to the frequency of said first and second pulse sequences; restarting said counting at a predetermined time instant in each cycle of said test signal, thereby creating a phase shifted third counting signal; frequency dividing said phase shifted third counting signal to a predetermined normalizing frequency, thereby creating a normalized signal having said predetermined normalizing frequency and a phase shift corresponding to the phase shift of said phase shifted third counting signal; and wherein said step of restarting said counting to create said first counting signal comprises restarting said counting to create said first and second counting signals, respectively, at predetermined time instants in alternate and remaining cycles of said normalized signal, respectively.

Claim 7

A method as set forth in claim 5, further comprising the step of synchronizing said normalized signal to said test signal.

Claim 8

Equipment for furnishing an error signal indicative of the deviation of the actual frequency of a test signal from a nominal frequency, comprising, in combination, high-frequency oscillator means for furnishing a high-frequency signal having a frequency substantially exceeding said nominal frequency of said test signal; first and second counting means, each having a counting input connected to said high-frequency oscillator means and a reset input, for counting the cycles of said high-frequency signal and furnishing, respectively, a first and second pulse sequence, each having a frequency substantially less than said frequency of said high-frequency signal but exceeding said nominal frequency; test circuit means having an input for receiving said test signal and an output connected to said reset input of one of said first and second counting means, for resetting said one counting means at time instants corresponding to predetermined time instants in the cycles of said test signal, whereby a phase shift is created between said first and second pulse Sequences; and logic circuit means having a first and second input respectively connected to said first and second counting means, and a logic circuit output, for receiving the so phase-shifted first and second pulse sequence and furnishing a third pulse sequence at said logic circuit output in response thereto, said third pulse sequence constituting said error signal.

Claim 9

Equipment for furnishing an error signal indicative of the deviation of the actual frequency of a test signal from a nominal frequency, comprising, in combination, high-frequency oscillator means for furnishing a high-frequency signal having a frequency substantially exceeding said nominal frequency of said test signal; first and second counting means, each having a counting input connected to said high-frequency oscillator means and a reset input, for counting the cycles of said high-frequency signal and furnishing, respectively, a first and second pulse sequence, each having a frequency substantially less than said frequency of said high-frequency signal but exceeding said nominal frequency; test circuit means having an input for receiving said test signal and an output connected to said reset input of one of said first and second counting means, for resetting said one counting means at time instants corresponding to predetermined time instants in the cycles of said test signal, whereby a phase shift is created between said first and second pulse Sequences; and logic circuit means having a first and second input respectively connected to said first and second counting means, and a logic circuit output, for receiving the so phase-shifted first and second pulse sequence and furnishing a third pulse sequence at said logic circuit output in response thereto, said third pulse sequence constituting said error signal.

Claim 10

A system as set forth in claim 1, wherein the output of said test circuit means is connected to the reset inputs of said first and second counting means for alternately resetting said first and second counting means, said third pulse sequence having a pulse only in the simultaneous presence of a pulse of said first sequence and the absence of a pulse of said second sequence.

Claim 11

A system as set forth in claim 8, wherein said logic circuit means comprises a NAND gate having a first input connected to said first counting means and a second input; and an inverter interconnected between said counting means and said second input of said NAND gate.

Claim 12

A system as set forth in claim 8, wherein said test circuit means comprise a bistable circuit having a first and second stable state; control circuit means having an output connected to said bistable circuit and an input for receiving said test signal, for switching said bistable circuit from said first to said second and said second to said first stable state at said predetermined time instants; and connecting means for connecting said bistable circuit to said reset inputs of said first and second counting means in such a manner that said first counting means is reset when said bistable circuit means switches from said first to said second stable state and that said second counting means is reset when said bistable circuit means switches from said second to said first stable state.

Claim 13

A system as set forth in claim 10, wherein said connecting means each comprise a differentiation circuit.

Claim 14

A system as set forth in claim 10, wherein the pulse width of the pulses of said third pulse sequence varies as a function of said deviation of said frequency of said test signal from said nominal frequency; further comprising a measuring instrument connected to said logic circuit output for furnishing a visual indication of said deviation.

Claim 15

A system as set forth in claim 12, wherein said measuring instrument has a centered zero position and a first and second input terminal; and wherein said logic circuit means comprise first logic circuit means having inputs connected to said first and second counting means and a first logic circuit output connected to said first terminal of said measuring instrument, for furnishing said third pulse sequence to said measuring instrument when said frequency of said test signal exceeds said nominal frequency, and second logic circuit means having inputs connected to said first and second counting means and a second logic circuit output connected to said second terminal of said measuring instrument, for furnishing said third pulse sequence to said measuring instrument when said actual frequency at said test signal is less than said nominal frequency, whereby the direction of deflection of said measuring instrument indicates whether said actual frequency of said test signal is less than or greater than said nominal frequency.

Claim 16

A system as set forth in claim 13, wherein said first and second counting means respectively have a first and second plurality of binary cascade-connected stages, each of said stages changing state at one half the frequency of the preceding one of said stages; wherein said first and second counting signals are the output of a corresponding selected one of said stages in said first and second counting means respectively; wherein said bistable circuit means has a first and second output terminal for furnishing an output signal when said bistable circuit means is in said first and second state respectively; and wherein said first logic circuit means comprise a first and second inverter rEspectively connected to the output of said first and second counting means, a first and second NAND gate, each of said NAND gates having four inputs and a NAND gate output, a third NAND gate having a first input connected to the output of said first NAND gate and a second input connected to the output of said second NAND gate, and a NAND gate output connected to said first terminal of said measuring instrument, and connecting means for connecting said four inputs of each of said NAND gates to said first and second inverter, said bistable circuit means and the stages preceding said selected ones of said stages in said first and second counting means in such a manner that said third NAND gate furnishes an output only when said actual frequency of said test signal is less than said nominal frequency.

Claim 17

A system as set forth in claim 14, wherein said second logic circuit means comprise a first and second inverter, a first and second NAND gate, each of said NAND gates having four inputs and a NAND gate output, a third NAND gate having a first input connected to the output of said first NAND gate, a second input connected to the output of said second NAND gate and a NAND gate output connected to said second terminal of said measuring instrument, and connecting means for connecting said four inputs of each of said first and second NAND gates to said bistable circuit means, the stages preceding said selected stages in said first and second counting means, and said first and second inverter in such a manner that said NAND gate output of said third NAND gate furnishes a signal to said measuring instrument only when said actual frequency of said test signal exceeds said nominal frequency.

Claim 18

A system as set forth in claim 8, wherein said test circuit means comprise high-frequency oscillator means for furnishing a high-frequency signal; first frequency divider means connected to said high-frequency oscillator means and having a reset input connected to receive said test signal, for furnishing a frequency divided signal having a frequency corresponding to the frequency of said high-frequency signal and a phase shift corresponding to said actual frequency of said test signal; and second frequency divider means connected to said first frequency divider means for furnishing a normalized test signal having a frequency independent of, but a phase shift corresponding to, said actual frequency of said test signal.

Claim 19

A system as set forth in claim 16, further comprising synchronizing circuit means connected to said second frequency divider means for synchronizing said normalized test signal to said test signal.

Claim 20

A system as set forth in claim 17, wherein said synchronizing circuit means comprise comparator means having a first input for receiving said test signal, a second input for receiving said normalized test signal, for resetting said second frequency divider means at a determined instant in the cycle of said test signal when said test signal and said normalized test signal are not in synchronism.