Patent US3895239A successfully refreshed from Google Patents.
US3895239A
Expired / Lapsed
US
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MOS power-on reset circuit
Assignee: Motorola Solutions Inc
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Filing: 1973-12-26
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Granted: 1975-07-15
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Expires: 1993-12-26
Abstract
Abstract An automatic power-on reset circuit adapted for use on complementary MOS integrated circuit semiconductor dies is provided. The circuit includes a voltage reference stage followed by an amplifier stage. A PN diode is coupled in series with a diode-connected MOSFET and a low current MOSFET device to provide a slight overdrive to the P-channel MOSFET of a CMOS inverter, which determines the initial output level thereof. As the voltage applied to the power supply conductor increases, the switching point of the amplifier-inverter stage varies until the output thereof assumes the opposite logic level. This transition of the output of the amplifier inverter stage is applied to wave shaping circuitry and an output circuit which reliably produces the desired reset signal.
Inventors
- 👤 Allan A Alaspa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 14:09
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/22; H03K17/223; H03K17/28; H03K17/284
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
113 words
An MOS automatic reset circuit coupled between first and second voltage conductors for producing a reset signal when a voltage applied between said first and second voltage conductors exceeds a particular magnitude comprising: a voltage reference circuit including a diode, a first MOSFET and a second MOSFET coupled in series between said first and second voltage conductors, said voltage reference circuit being for providing a reference voltage approximately equal in magnitude to the sum of the voltage drops across said diode and said second MOSFET: a complementary MOS inverter circuit coupled between said first and second voltage conductors having an input coupled to the gate electrode and drain electrode of said second MOSFET.
Claim 2
Dependent Claim
113 words
An MOS automatic reset circuit coupled between first and second voltage conductors for producing a reset signal when a voltage applied between said first and second voltage conductors exceeds a particular magnitude comprising: a voltage reference circuit including a diode, a first MOSFET and a second MOSFET coupled in series between said first and second voltage conductors, said voltage reference circuit being for providing a reference voltage approximately equal in magnitude to the sum of the voltage drops across said diode and said second MOSFET: a complementary MOS inverter circuit coupled between said first and second voltage conductors having an input coupled to the gate electrode and drain electrode of said second MOSFET.
Claim 3
Dependent Claim
51 words
The MOS automatic reset circuit as recited in claim 1 further including a wave shaping circuit coupled to an output of said complementary MOS inverter, said wave shaping circuit being for providing an output signal on an output node of said MOS automatic reset circuit coupled to said wave shaping circuit.
Claim 4
Dependent Claim
99 words
The MOS automatic reset circuit as recited in claim 2, said voltage reference circuit including a third MOSFET, said diode having its anode coupled to said first voltage conductor and its cathode coupled to the source electrode of said first MOSFET, said first MOSFET being P-channel and having its drain coupled to the source of said second MOSFET, said second MOSFET being P-channel and having its drain coupled to the input of said complementary MOS inverter, and to the drain of said third MOSFET, said third MOSFET being N-channel and having its source coupled to said second voltage conductor.
Claim 5
Dependent Claim
141 words
The MOS automatic reset circuit as recited in claim 3 wherein said wave shaping circuit includes second and third complementary MOS inverters cascaded with said first complementary MOS inverter and an output circuit including a fourth and fifth MOSFET coupled in series between said first and second voltage conductors, said fourth MOSFET being P-channel and said fifth MOSFET being N-channel, the source of said fourth MOSFET being coupled to said first voltage conductor and the drain of said fourth MOSFET being coupled to the drain of said fifth MOSFET, said fifth MOSFET having its source coupled to said second voltage conductor and its gate coupled to an output of said third complementary MOS inverter and also to the gate electrode of said fourth MOSFET, the drain of said fifth MOSFET being coupled to an output node of said automatic reset circuit.
Claim 6
Dependent Claim
43 words
The MOS automatic reset circuit as recited in claim 2 including a disable circuit for disabling said voltage reference circuit coupled between said first and second voltage conductors and a master reset circuit coupled to said output circuit and said voltage reference circuit.
Claim 7
Dependent Claim
123 words
The MOS automatic reset circuit as recited in claim 5 wherein said master reset circuit includes a sixth P-channel MOSFET coupled between the drain of said fifth MOSFET and the drain of said fourth MOSFET and having its gate electrode coupled to a master reset control conductor and to the gate electrode of said first MOSFET; said disable circuit including an seventh P-channel MOSFET having its source coupled to said first voltage conductor and its drain coupled to the input of said first amplifier circuit, a fourth complementary MOS inverter coupled between said first and second voltage conductors having its input coupled to a reset disable conductor and its output coupled to the gate electrode of said third MOSFET and said seventh MOSFET.
Claim 8
Dependent Claim
27 words
The MOS automatic reset circuit as recited in claim 3 further including a capacitor coupled between an input of said second inverter and said first voltage conductor.
Claim 9
Dependent Claim
27 words
The MOS automatic reset circuit as recited in claim 3 further including a capacitor coupled between the input of said first inverter and said second voltage conductor.
Claim 10
Dependent Claim
26 words
The MOS automatic reset circuit as recited in claim 2 further including a one-shot circuit coupled to an output node of said MOS automatic reset circuit.
Claim 11
Dependent Claim
27 words
The MOS automatic reset circuit as recited in claim 1 on an integrated MOS semiconductor die providing a reset signal to additional circuitry On said semiconductor die.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-07-14 | 1979-01-13 | 1979-07-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-07-14 | 1983-01-13 | 1983-07-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-07-14 | 1987-01-13 | 1987-07-15 | $7700.00 | Window Closed / Lapsed |