US3894891A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for making a space charge limited transistor having recessed dielectric isolation
Assignee: International Business Machines Corp
•
Filing: 1974-05-28
•
Granted: 1975-07-15
•
Expires: 1994-05-28
Abstract
Abstract A space charge limited transistor formed on a high resistivity substrate of at least 10,000 ohm-centimeter silicon of one conductivity type. One surface of the substrate is provided with spaced recessed oxide regions. The alternate spaces between the oxide regions are occupied by impurity zones of said one conductivity type. The intervening alternate spaces between the oxide regions are occupied by impurity zones of the other conductivity type. The impurity concentrations of the aforesaid impurity zones are at least several orders of magnitude higher than that of the substrate where the zones are separated from each other by the aforesaid oxide regions. The dielectric relaxation time is much larger than the carrier transit time within the substrate below and between adjacent impurity zones of the same conductivity type.
Inventors
- 👤 Ingrid E Magdo
- 👤 Steven Magdo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 04:59
CPC Classifications
H; H10; H10D; H10D99/00; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/012; H10W10/10; H10W10/13; Y; Y10; Y10S; Y10S148/00; Y10S148/085; Y10S148/117; Y10S148/122
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
83 words
A METHOD FOR SIMULTANEOUSLY PRODUCING NPN AND PNP SPACE CHARGE LIMITED TRANSISTORS COMPRISING: PROVIDING A HIGH RESISTIVITY SUBSTRATE OF AT LEAST 10,000 OHMCENTIMETER SEMICONDUCTOR MATERIAL, FORMING SPACED RECESSED DIELECTRIC REGIONS EXTENDING FROM SAID ONE SURFACE OF SAID SUBSTRATE INTO THE INTERIOR THEREOF, FORMING IN ALTERNATE SPACES BETWEEN SAID REGIONS FIRST IMPURITY ZONES OF ONE CONDUCTIVITY TYPE EXTENDING FROM ONE SURFACE OF SAID SUBSTRATE INTO HE INTERIOR THEREOF, FORMING IN THE INTERVENING ALTERNATE SPACES BETWEEN SAID REGIONS SECOND IMPURITY ZONES OF THE OTHER CONDUCTIVITY
Claim 2
Independent Claim
83 words
A METHOD FOR SIMULTANEOUSLY PRODUCING NPN AND PNP SPACE CHARGE LIMITED TRANSISTORS COMPRISING: PROVIDING A HIGH RESISTIVITY SUBSTRATE OF AT LEAST 10,000 OHMCENTIMETER SEMICONDUCTOR MATERIAL, FORMING SPACED RECESSED DIELECTRIC REGIONS EXTENDING FROM SAID ONE SURFACE OF SAID SUBSTRATE INTO THE INTERIOR THEREOF, FORMING IN ALTERNATE SPACES BETWEEN SAID REGIONS FIRST IMPURITY ZONES OF ONE CONDUCTIVITY TYPE EXTENDING FROM ONE SURFACE OF SAID SUBSTRATE INTO HE INTERIOR THEREOF, FORMING IN THE INTERVENING ALTERNATE SPACES BETWEEN SAID REGIONS SECOND IMPURITY ZONES OF THE OTHER CONDUCTIVITY
Claim 3
Dependent Claim
13 words
The method of claim 1 wherein said impurity zones are produced by diffusion.
Claim 4
Dependent Claim
14 words
The method of claim 1 wherein said impurity zones are formed by ion implantation.
Claim 5
Dependent Claim
17 words
The method of claim 1 wherein said impurity zones are formed by one of alloying and sintering.
Claim 6
Dependent Claim
18 words
The method of claim 1 wherein said recessed dielectric regions are formed by recessed oxidation of said substrate.
Claim 7
Dependent Claim
32 words
The method of claim 1 wherein said recessed dielectric regions are formed by placing grooves in said one surface of said substrate and covering the surface of said grooves with dielectric material.
Claim 8
Dependent Claim
41 words
The method of claim 1 and further forming along interconnection pathways between said transistors another recessed dielectric region extending from said one surface of said substrate into the interior thereof, and placing a metalization line on said another recessed dielectric region.
Claim 9
Dependent Claim
18 words
The method of claim 1 wherein said recessed dielectric regions are formed after said first zones are formed.
Claim 10
Dependent Claim
21 words
The method of claim 1 wherein said recessed dielectric regions are formed after said first and said second zones are formed.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-07-14 | 1979-01-13 | 1979-07-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-07-14 | 1983-01-13 | 1983-07-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-07-14 | 1987-01-13 | 1987-07-15 | $7700.00 | Window Closed / Lapsed |