Patent US3894246A successfully refreshed from Google Patents.
US3894246A
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Clock recovering apparatus and method
Assignee: Boeing North American Inc
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Filing: 1974-06-24
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Granted: 1975-07-08
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Expires: 1994-06-24
Abstract
Abstract A circuit for generating a clock based on time of receipt of a RZ (return to zero) data bit stream using a known clocking frequency. An internal actuated counter is used to generate a lower frequency data clock and is reset to an initial condition whenever the incoming data phase deviates mote than a prescribed amount from the phase of the generated clock. A non-zero data pattern is required to periodically resynchronize the derived clock with the incoming data.
Inventors
- 👤 Willard J Torgrim
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 18:22
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/0054; H04L7/0066; H03; H03K; H03K5/00; H03K5/13; H03K5/135
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
268 words
Apparatus for recovering a clock signal from received data comprising, in combination: data means for supplying input data signals; high frequency clock means for supplying high frequency clock signals having continuously alternating logic 1 and logic zero values; first flip-flop means including input and output means; second flip-flop means including clock, input and output means; first logic means connected to said data means, said clock means, said output means of said second flip-flop means and to said first flop means for setting said first flip-flop in response to a first predetermined set of input signals from said data means, said clock means and said output means of second flip-flop means and for resetting said first flip-flop means in response to a second predetermined set of input signals; counter means, including clock input and clock output means for providing a data clock output signal at a divided and lower frequency than the input; means connecting the high frequency clock means to said clock input means of said counter means; second logic means, connected between said counter means and said second flip-flop means for setting said second flip-flop at a predetermined count; third logic means connected to said first and said second flip-flop means for actuating said second flip-flop means in response to a third predetermined set of input signal conditions; fourth logic means, connected to said counter means, said clock means, said first flip-flop means and said second flip-flop means, for initializing said counter in response to a fourth predetermined set of input conditions; and data signal output means connected to said output means of said second flip-flop means.
Claim 2
Dependent Claim
268 words
Apparatus for recovering a clock signal from received data comprising, in combination: data means for supplying input data signals; high frequency clock means for supplying high frequency clock signals having continuously alternating logic 1 and logic zero values; first flip-flop means including input and output means; second flip-flop means including clock, input and output means; first logic means connected to said data means, said clock means, said output means of said second flip-flop means and to said first flop means for setting said first flip-flop in response to a first predetermined set of input signals from said data means, said clock means and said output means of second flip-flop means and for resetting said first flip-flop means in response to a second predetermined set of input signals; counter means, including clock input and clock output means for providing a data clock output signal at a divided and lower frequency than the input; means connecting the high frequency clock means to said clock input means of said counter means; second logic means, connected between said counter means and said second flip-flop means for setting said second flip-flop at a predetermined count; third logic means connected to said first and said second flip-flop means for actuating said second flip-flop means in response to a third predetermined set of input signal conditions; fourth logic means, connected to said counter means, said clock means, said first flip-flop means and said second flip-flop means, for initializing said counter in response to a fourth predetermined set of input conditions; and data signal output means connected to said output means of said second flip-flop means.
Claim 3
Dependent Claim
39 words
Apparatus as claimed in claim 1 wherein: said first logic means comprises a NAND gate and three NOR gates; said second and fourth logic means each comprises a NAND gate; and said third logic means comprises a NOR gate.
Claim 4
Independent Claim
168 words
The method of producing a clock having the proper phase relationship with respect to a received data signal, comprising the steps of: generating a high frequency clock signal; counting the high frequency clock signal for dividing it to a lower frequency signal; generating a logic first signal upon the simultaneous occurrence of a high frequency clock of a given first logic value and a given second logic value of an incoming data signal occurring after a minimum period of time of not receiving a data signal of the second logic value; generating a logic 1 output data signal upon the next occurrence of a high frequency clock of the given first logic value only if the incoming data signal has remained at the second logic value; setting the counting means to an initial condition after the generation of an output data signal; and, returning the logic 1 output data signal to a logic zero at a predetermined count of the means for counting the high frequency clock signal.
Claim 5
Independent Claim
168 words
The method of producing a clock having the proper phase relationship with respect to a received data signal, comprising the steps of: generating a high frequency clock signal; counting the high frequency clock signal for dividing it to a lower frequency signal; generating a logic first signal upon the simultaneous occurrence of a high frequency clock of a given first logic value and a given second logic value of an incoming data signal occurring after a minimum period of time of not receiving a data signal of the second logic value; generating a logic 1 output data signal upon the next occurrence of a high frequency clock of the given first logic value only if the incoming data signal has remained at the second logic value; setting the counting means to an initial condition after the generation of an output data signal; and, returning the logic 1 output data signal to a logic zero at a predetermined count of the means for counting the high frequency clock signal.
Claim 6
Dependent Claim
185 words
Apparatus for producing a clock signal having the proper phase relationship with respect to a received data signal comprising, in combination: means for generating a high frequency clock signal; means for counting the high frequency clock signal whereby it is divided to a lower frequency clock signal; means for generating a logic 1 first signal upon the simultaneous occurrence of a high frequency clock signal of a given first logic value and of an incoming data signal occurring after a minimum period of time of not receiving a data signal value of the second logic value; means for generating a logic 1 output data signal upon the next occurrence of the high frequency clock having the given first logic value only if the incoming data signal has remained at the second logic value; means for setting the counting means to an initial condition after the generation of an output data signal of the logic 1 value; and means for returning the Logic 1 value output data signal to a logic zero at a predetermined count of the means for counting the high frequency clock signal.
Claim 7
Dependent Claim
185 words
Apparatus for producing a clock signal having the proper phase relationship with respect to a received data signal comprising, in combination: means for generating a high frequency clock signal; means for counting the high frequency clock signal whereby it is divided to a lower frequency clock signal; means for generating a logic 1 first signal upon the simultaneous occurrence of a high frequency clock signal of a given first logic value and of an incoming data signal occurring after a minimum period of time of not receiving a data signal value of the second logic value; means for generating a logic 1 output data signal upon the next occurrence of the high frequency clock having the given first logic value only if the incoming data signal has remained at the second logic value; means for setting the counting means to an initial condition after the generation of an output data signal of the logic 1 value; and means for returning the Logic 1 value output data signal to a logic zero at a predetermined count of the means for counting the high frequency clock signal.
References Cited (Backward Citations)
US3363183A
Cited
US3440547A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-07-07 | 1979-01-06 | 1979-07-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-07-07 | 1983-01-06 | 1983-07-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-07-07 | 1987-01-06 | 1987-07-08 | $7700.00 | Window Closed / Lapsed |