Patent US3893151A successfully refreshed from Google Patents.
US3893151A
Expired / Lapsed
US
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Semiconductor memory device and field effect transistor suitable for use in the device
Assignee: US Philips Corp
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Filing: 1973-06-07
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Granted: 1975-07-01
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Expires: 1993-06-07
Abstract
Abstract Semiconductor memory device in which charge carriers are injected between a semiconductor surface and a gate electrode separated from the semiconductor surface by an insulating layer to effect a change in the characteristics of the device. According to the invention for the storage of information a depletion zone is formed across which a voltage drop is applied which is lower than the voltage at which avalanche multiplication occurs, but higher than the potential barrier for the charge carriers at the interface between the insulating layer and the semiconductor material, while charge carriers are injected into this depletion zone by means of a p-n junction or by radiation.
Inventors
- 👤 Cornelis Albertus Bosselaar
- 👤 Olof Erik Hans Klaver
- 👤 Jan Florus Verwey
- 👤 Santen Johannes Gerrit Van
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 18:22
CPC Classifications
H; H10; H10B; H10B69/00; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/684; H10D30/685
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
180 words
A semiconductor memory device comprising: a. a semiconductor body comprising a first region that is adjacent to the surface of said body, b. an electrically insulating layer that at least partly covers said first region, c. a gate electrode disposed over said semiconductor body surface and separated therefrom by said insulating layer, d. means for forming a depletion zone adjacent to said insulating layer in said first region below the gate electrode, whereby charge carriers can be injected from said semiconductor body into said insulating layer and the electrical properties of said device thereby changed, said depletion zone forming means comprising means for providing across said depletion zone a voltage drop that is lower than the voltage at which avalanche multiplication occurs, but higher than the potential barrier for said charge carriers at the interface between said semiconductor body and said insulating layer, e. means for injecting said charge carriers into said depletion zone, and f. means for simultaneously applying a voltage to said gate electrode to exert on said charge carriers a force in the direction of said interface.
Claim 2
Dependent Claim
180 words
A semiconductor memory device comprising: a. a semiconductor body comprising a first region that is adjacent to the surface of said body, b. an electrically insulating layer that at least partly covers said first region, c. a gate electrode disposed over said semiconductor body surface and separated therefrom by said insulating layer, d. means for forming a depletion zone adjacent to said insulating layer in said first region below the gate electrode, whereby charge carriers can be injected from said semiconductor body into said insulating layer and the electrical properties of said device thereby changed, said depletion zone forming means comprising means for providing across said depletion zone a voltage drop that is lower than the voltage at which avalanche multiplication occurs, but higher than the potential barrier for said charge carriers at the interface between said semiconductor body and said insulating layer, e. means for injecting said charge carriers into said depletion zone, and f. means for simultaneously applying a voltage to said gate electrode to exert on said charge carriers a force in the direction of said interface.
Claim 3
Dependent Claim
51 words
A semiconductor memory device as in claim 1, comprising a rectifying junction that is located at said first region and ends at said interface below said gate electrode, and means for temporarily applying a reverse voltage across said rectifying junction so as to form at least part of said depletion zone.
Claim 4
Dependent Claim
34 words
A semiconductor memory device as in claim 2, comprising a p-n junction that is adapted to be temporarily biased in the forward direction, whereby said charge carriers can be injected into said depletion zone.
Claim 5
Dependent Claim
46 words
A semiconductor memory device as in claim 1, comprising means for temporarily applying a voltage between said gate electrode and said first region such that majority carriers are removed from a surface zone of said first region, thereby forming at least part of said depletion zone.
Claim 6
Dependent Claim
32 words
A semiconductor memory device as in claim 4, whereIn the distance between said p-n junction and said rectifying junction is at most one diffusion length of the charge carriers in said region.
Claim 7
Dependent Claim
38 words
A semiconductor memory device as in claim 1, comprising means for temporarily impinging radiation on said semiconductor body, whereby said radiation generates electron-hole pairs in said depletion zone and said charge carriers are injected into said depletion zone.
Claim 8
Dependent Claim
55 words
A semiconductor memory device as in claim 1, comprising an insulated gate field-effect transistor that includes said gate electrode and said insulating layer and further comprises source and drain electrodes and a channel area therebetween, said depletion zone being formed in channel area of said transistor, said channel area being disposed in said first region.
Claim 9
Dependent Claim
43 words
A semiconductor memory device as in claim 7, wherein said field-effect transistor is one of the depletion type and the enhancement type and is adapted to be converted into a transistor of the other type by the injection of information-carrying said charge carriers.
Claim 10
Dependent Claim
70 words
A semiconductor memory device as in claim 7, wherein said field-effect transistor comprises a layer-shaped said channel area of said first conductivity type disposed adjacent to said body surface and an underlying region of second conductivity type, said channel area and said underlying region forming a p-n junction that is adapted to be temporarily forward biased and is substantially parallel to said surface and comprises said charge carrier injecting means.
Claim 11
Dependent Claim
43 words
A semiconductor memory device as in claim 7, comprising an electrically floating conductive layer disposed between said gate electrode and said semiconductor surface and separated from both thereof by portions of said insulating layer located between said gate electrode and said semiconductor surface.
Claim 12
Dependent Claim
17 words
A semiconductor memory device as in claim 10, wherein said conductive layer consists essentially of polycrystalline silicon.
Claim 13
Dependent Claim
45 words
A semiconductor memory device as in claim 2, wherein said insulating layer disposed between said gate electrode and semiconductor body surface comprises at least two layers respectively consisting essentially of silicon oxide and silicon nitride, one of said layers being disposed on top of another.
Claim 14
Dependent Claim
47 words
A semiconductor memory device as in claim 1, comprising a bipolar transistor that includes an emitter-base junction adapted to be temporarily biased in the reverse direction and a collector-base junction adapted to be temporarily biased in forward direction, said collector-base junction comprising said charge carrier injecting means.
Claim 15
Dependent Claim
61 words
A semiconductor memory device as in claim 1, wherein the semiconductor material of said semiconductor body consists essentially of silicon and at least the part of said insulating layer adjacent to said body surface consists essentially of silicon dioxide, wherein said depletion zone forming means provides said voltage drop across the depletion zone that is at least equal to 4 volts.
Claim 16
Dependent Claim
94 words
A semiconductor memory device as in claim 1, wherein said injection of said charge carriers into said insulating layer provides stored information and said device comprises a rectifying junction that is located at said first region and ends at said interface below said gate electrode, and means for temporarily applying a reverse voltage across said rectifying junction so as to form at least part of said depletion zone and further comprises means for temporarily biasing said rectifying junction in reverse direction so as to produce avalanche multiplication, whereby said stored information can be erased.
Claim 17
Dependent Claim
126 words
An insulated gate electrode field-effect transistor with suitable for use in a semiconductor memory device, comprising a semiconductor body with a layer-shaped channel area of a first conductivity type adjacent to a surface of said body, a second region of second conductivity type underlying said channel area and forming therewith a p-n junction, source and drain electrodes adjacent to said surface, an insulating laYer present on said semiconductor body surface at least between said source and drain electrodes, a gate electrode disposed over said semiconductor surface and separated therefrom by said insulating layer, and an electrically floating conductive layer disposed between said gate electrode and said body surface, said conductive layer being separated from said gate electrode and said semiconductor body surface by said insulating layer.
Claim 18
Dependent Claim
126 words
An insulated gate electrode field-effect transistor with suitable for use in a semiconductor memory device, comprising a semiconductor body with a layer-shaped channel area of a first conductivity type adjacent to a surface of said body, a second region of second conductivity type underlying said channel area and forming therewith a p-n junction, source and drain electrodes adjacent to said surface, an insulating laYer present on said semiconductor body surface at least between said source and drain electrodes, a gate electrode disposed over said semiconductor surface and separated therefrom by said insulating layer, and an electrically floating conductive layer disposed between said gate electrode and said body surface, said conductive layer being separated from said gate electrode and said semiconductor body surface by said insulating layer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-06-30 | 1978-12-30 | 1979-07-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-06-30 | 1982-12-30 | 1983-07-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-06-30 | 1986-12-30 | 1987-07-01 | $7700.00 | Window Closed / Lapsed |