Sweep and memory control circuit

Claim 2

A digital sweep voltage generator for providing sweep voltages to a doppler satellite tracking station receiver voltage-controlled oscillator to ensure searching in the correct doppler frequency range at a proper rate, comprising: a. means for generating a continuous train of identical ramp function signals having an output; b. a first digital-to-analog converter circuit having an input circuit and an output; c. means for providing an enable signal; d. means for providing a manually-set digital signal; e. means for gating said manually-set digital signal to said input circuit of said first digital-to-analog converter circuit when said enable signal is at a logic 0 level, said means for providing an enable signal being connected to said means for gating said manually-set digital signal; f. means for providing a doppler frequency signal having an output; g. means for generating a digital signal that is a function of the frequency of said doppler frequency signal having an output circuit and an input, said input being connected to said output of said means for providing a doppler frequency signal; h. means for gating said digital signal that is a function of the frequency of said doppler frequency signal to said input circuit of said first digital-to-analog converter circuit when said enable signal is at a logic 1 level, said means for providing an enable signal being connected to said means for gating said digital signal that is a function of the frequency of said doppler frequency signal, said means for gating said digital signal that is a function of the frequency of said doppler frequency signal having an input circUit and an output circuit; i. a voltage combiner circuit having a first and a second input and an output, said output of said digital-to-analog converter circuit being connected to said first input, said output of said means for generating a continuous train of identical ramp function signals being connected to said second input, said output being said sweep voltage for said doppler satellite tracking station receiver.

Claim 3

The generator of claim 1 wherein the means for generating a continuous train of identical ramp function signals comprises: a. means for providing a reference frequency signal; b. a counter circuit having an input and an output circuit, said reference frequency signal being connected to said input; c. a second digital-to-analog converter circuit having an output and an input circuit, said output circuit of said counter circuit being connected to said input circuit, said second digital-to-analog converter circuit output providing said train of identical ramp-function signals.

Claim 4

The generator of claim 1 wherein said first digital-to-analog converter circuit comprises: a. a first digital-to-analog converter having a plurality of inputs and an output, said output being connected to said input of said voltage combiner circuit, and b. means for gating said manually-set digital signal and said digital signal that is a function of the frequency of said doppler-frequency signal from said input circuit to said plurality of inputs.

Claim 5

The generator of claim 1 wherein said means for generating a digital signal that is a function of the frequency of said doppler frequency signal includes a memory circuit for remembering said digital signal that is a function of the frequency of said doppler frequency signal whereby said doppler satellite tracking station is capable of continued searching in the correct doppler frequency range.

Claim 6

The generator of claim 1 wherein said means for generating a digital signal that is a function of the frequency of said doppler frequency signal comprises: a. a multiple-bit binary counter circuit having a first and a second input and a plurality of outputs; b. a first gate circuit having an output and a first and a second input, said output being connected to said first input of said counter circuit, said first input of said gate circuit being connected to said output of said means for providing a doppler frequency signal; c. a storage register having a plurality of inputs connected to said plurality of outputs of said counter circuit such that said counter circuit and said storage register are in parallel, said storage register having a plurality of outputs connected to said plurality of inputs of said means for gating said digital signal that is a function of the frequency of said doppler frequency signal such that said storage register and said means for gating said digital signal that is a function of the frequency of said doppler-frequency signal are in parallel, said storage register also having a clock input; d. means for providing a low-frequency signal having an output; e. means for providing a doppler-frequency correlation signal having an output; f. a circuit for generating control signals having a low-frequency signal input, a doppler-frequency correlation input, a gate signal output, a reset signal output and a clock signal output, said low-frequency input being connected to said output of said means for providing a low-frequency signal, said doppler-frequency correlation input being connected to said output of said means for providing a doppler-frequency correlation signal, said gate signal output being connected to said second input of said gate circuit whereby said gate circuit is enabled when a control signal is at a logic 1 level on said gate signal output, said reset signal output being connected to said second input to said counter circuit whereby said counter circuit is reset when a control signal is present on said reset signal output, saId clock signal output being connected to said clock input of said storage register wherein said storage register shifts the contents of said counter circuit into itself only when a control signal is present on said clock signal output.

Claim 7

The generator of claim 5 wherein said circuit for generating control signals comprises: a. a flip-flop having an input and a first and a second output, said input being connected to said output of said means for providing a low-frequency signal, said first output being said gate signal output; b. a monostable multivibrator having an input and an output, said input being connected to said second output of said flip-flop, said output being said reset signal output; c. a second gate circuit having a first and a second input and an output, said first input being connected to said second output of said flip-flop, said second input being connected to said output of said means for providing a doppler frequency correlation signal, said output being said clock signal output, said doppler frequency correlation signal preventing a control signal from appearing on said clock signal output when said doppler frequency correlation signal is at a logic 0 level whereby said shift register retains its contents whereby said storage register remembers said digital signal that is a function of the frequency of said doppler frequency signal.

Claim 8

The generator of claim 5 wherein said plurality of outputs of said multiple-bit counter are fewer in number than the number of bits of said multiple-bit counter.